參數(shù)資料
型號： M37641M8-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 42/149頁
文件大?。?/td> 1997K
代理商： M37641M8-XXXFP
42
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
(2) Burst Transfer Mode
When the DMAC Channel x Transfer Mode Selection Bit (DxTMS)
is set to
“
1
”
, the respective DMAC channel operates in the burst
transfer mode.
In the burst transfer mode, the DMAC continually transfers the
number of bytes of data specified by the Transfer Count Register
for one transfer request. Other than this, the burst transfer mode
operation is the same as the cycle steal mode operation.
Priority
The DMAC places a higher priority on Channel-0 transfer requests
than on Channel-1 transfer requests.
If a Channel-0 transfer request occurs during a Channel-1 burst
transfer operation, the DMAC completes the next transfer source
and destination read/write operation first, and then starts the
Channel-0 transfer operation. As soon as the Channel-0 transfer is
completed, the DMAC resumes the Channel-1 transfer operation.
When an interrupt request occurs during any DMA operation, the
transfer operation is suspended and the interrupt process routine
is initiated. During the interrupt operation, the DMAC automatically
sets the corresponding DMAC Channel x (x = 0, 1) Flag to
“
1
”
. As
soon as the CPU completes the interrupt operation, the DMAC
clears the flag to
“
0
”
and resumes the original operation from the
point where it was suspended.
The suspended transfer due to the interrupt can also be resumed
during its interrupt process routine by writing
“
1
”
to the DMAC
Channel x (x = 0,1) Enable Bit (DxCEN).
The timing charts for a burst transfer caused by a hardware-re-
lated transfer request are shown in Figure 35.
Fig. 35 Timing chart for burst transfer caused by hardware-related transfer request
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