參數(shù)資料
型號(hào)： M37641M8-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 4/149頁
文件大小： 1997K
代理商： M37641M8-XXXFP
4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
P5
0
/X
CIN
,
P5
1
/T
OUT
/
X
COUT
,
P5
2
/OBF
0
,
P5
3
/IBF
0
,
P5
4
/S
0
,
P5
5
/A
0
,
P5
6
/R(E),
P5
7
/W(R/W)
Apply 4.15 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to the Vcc pin. Apply 0 V to the
Vss pin.
This controls the MCU operating mode. Connect this pin to Vss. If connecting this pin to Vcc, the
internal ROM is inhibited. In the flash memory version this pin functions as a V
PP
power supply input pin.
These pins are the power supply inputs for analog circuitry.
Reset input pin for active “L.”
Connect a ceramic resonator or a quartz-crystal oscillator between the X
IN
and X
OUT
pins to set the
oscillation frequency.
If an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
Loop filter for the frequency synthesizer.
Power supply input pin for 3.3 V USB line driver.
USB D+ voltage signal port. Connect a 27 to 33
(recommended) resistor in series.
USB D- voltage signal port. Connect a 27 to 33
(recommended) resistor in series.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
When connecting an external memory, these function as the address bus.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
When connecting an external memory, these function as the address bus.
8-bit I/O port.
CMOS compatible input level or VIHL input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
When connecting an external memory, these function as
the data bus.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
When connecting an external memory, these function as
the control bus.
Key-on wake-up interrupt input pin
V
CC
, V
SS
CNVss/V
PP
AVss/AVcc
RESET
X
IN
X
OUT
LPF
Ext. Cap.
USB D+
USB D-
P0
0
/AB
0
–
P0
7
/AB
7
Name
Power source
CNVss
Analog power
supply
Reset input
Clock input
Clock output
LPF
3.3 V line power
supply
USB D+
USB D-
I/O port P0
Function except a port function
PIN DESCRIPTION
Table 1 Pin description (1)
Function
P1
0
/AB
8
–
P1
7
/AB
15
P2
0
/DB
0
–
P2
7
/DB
7
P3
0
/RDY,
P3
1
, P3
2
,
P3
3
/DMA
OUT
,
P3
4
/
φ
OUT
,
P3
5
/SYNC
OUT
,
P3
6
/WR,
P3
7
/RD
P4
0
/EDMA,
P4
1
/INT
0
,
P4
2
/INT
1
,
P4
3
/CNTR
0
,
P4
4
/CNTR
1
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
When connecting an external memory, these function as
the control bus.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
When enabling the Master CPU bus interface function,
CMOS or TTL input level can be selected as an input.
I/O port P1
I/O port P2
I/O port P3
(See Remarks.)
I/O port P4
External memory control pin
I/O port P5
External memory control pin
External interrupt pin
Timer X, Timer Y pin
Sub-clock generating input pin
Timers 1, 2 pulse output pins
Sub-clock generating output pin
Master CPU bus interface pin
Pin
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