參數(shù)資料
型號： M37641M8-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 125/149頁
文件大?。?/td> 1997K
代理商： M37641M8-XXXFP
125
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started by connecting
“
H
”
to the P8
1
(SCLK) pin
and
“
H
”
to the CNV
SS
pin (apply 4.5 V to 5.25 V to Vpp from an
external source), and releasing the reset operation. (In the ordi-
nary microcomputer mode, set CNVss pin to
“
L
”
level.)
This control program is written in the Boot ROM area when the
product is shipped from Mitsubishi. Accordingly, make note of the
fact that the standard serial I/O mode cannot be used if the Boot
ROM area is rewritten in parallel I/O mode. Figures 102 and 103
show the pin connections for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK, SRXD, STXD and SRDY (BUSY). The SCLK pin is the
transfer clock input pin through which an external transfer clock is
input. The STXD pin is for CMOS output. The SRDY (BUSY) pin
outputs
“
L
”
level when ready for reception and
“
H
”
level when re-
ception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 104 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
Outline Performance (Standard Serial I/O
Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O.
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK pin, and are then input to the MCU via the SRXD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the STXD pin.
The STXD pin is for CMOS output. Transfer is in 8-bit units with
LSB first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY (BUSY) pin is
“
H
”
level. Accordingly,
always start the next transfer after the SRDY (BUSY) pin is
“
L
”
level.
Also, data and status registers in a memory can be read after in-
putting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
N
o
t
e
s
1
:
T
a
T
h
r
e
o
e
a
s
B
s
p
o
i
e
o
i
t
i
f
R
h
a
O
i
b
M
i
t
b
l
a
d
c
r
.
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)
,
a
c
a
n
b
e
r
e
w
r
i
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t
e
n
i
n
o
n
l
y
p
a
r
a
l
l
e
l
I
/
O
m
o
d
e
.
(
A
c
c
e
s
s
t
o
a
n
y
o
t
h
e
r
s
c
n
y
e
o
2
:
u
s
e
t
h
e
m
a
x
i
m
u
m
a
d
d
r
e
s
s
i
n
t
h
e
b
l
o
c
k
.
CPU rewrite mode, standard serial I/O mode
U
s
e
r
a
r
e
a
/
B
o
o
t
a
r
e
a
s
e
l
e
c
t
b
i
t
=
“
0
”
User area / Boot area select bit =
“
1
”
E000
16
FFFF
16
U
s
e
r
R
O
M
a
r
e
a
4
Kb
y
t
e
B
o
o
t
R
O
M
a
r
e
a
C000
16
Block 1 : 8 Kbytes
Block 2 : 16 Kbytes
Block 0 : 8 Kbytes
8000
16
F000
16
FFFF
16
Fig. 104 Block digram of on-chip flash memory
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參數(shù)描述
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M3-7643A-S 制造商:Harris Corporation 功能描述:
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