參數(shù)資料
型號(hào)： M37640M8-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 59/96頁(yè)
文件大?。?/td> 1477K
代理商： M37640M8-XXXFP
62
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The USB Endpoint x OUT CSR (Control & Status
Register), shown in Figure 1.65, contains control and
status information of the respective OUT endpoint 1-
4. The USB Endpoint Index Register selects the
specific endpoint.
OUTXCSR0 (OUT_PKT_RDY): The USB FCU sets
this bit to a “1” after it successfully receives a packet
of data from the host. This bit is cleared by the CPU
or by the USB FCU after a packet of data has been
unloaded from the FIFO (See section 1.21.3.2 for de-
tails).
OUTXCSR1 (OVER_RUN): This bit is used in ISO
mode only to indicate to the CPU that a FIFO overrun
has occurred. The USB FCU sets this bit to a “1” at
the beginning of an OUT token if the OUTXCSR0
(OUT_PKT_RDY) bit is not cleared. Setting this bit
will cause the INST12 bit of the Interrupt Status Reg-
ister 2 to set. The CPU writes a “0” to clear this bit.
OUTXCSR2 (SEND_STALL): The CPU writes a “1”
to this bit when the endpoint is stalled (receiver halt).
The USB FCU returns a STALL handshake while this
bit is set. The CPU writes a “0” to clear this bit.
OUTXCSR3 (ISO/TOGGLE_INIT): When the end-
point is used for isochronous data transfer, the CPU
sets this bit to a “1” for the entire duration of the iso-
chronous transfer. With the ISO bit set to a “1”, the
device accepts either DATA0 or DATA1 for the PID
sent by the host.
When the endpoint is required to initialize the data
toggle sequence bit (reset to DATA0 for the next data
packet), the CPU sets this bit to a “1” and then resets
it to a “0” to initialize the respective endpoint’s data
toggle.
As with any other method to initialize the data toggle,
this set/reset of the TOGGLE_INIT bit method as-
sumes that there is no active OUT transaction to the
respective endpoint on the bus at the time the initial-
ization process is ongoing. Set/reset of the
TOGGLE_INIT bit is performed only when an end-
point experiences a configuration event.
OUTXCSR4 (FORCE_STALL): The USB FCU sets
this bit to a “1” if the host sends out a larger data
packet than the MAXP size. The USB FCU returns a
STALL handshake while this bit is set. The CPU
writes a “0” to clear this bit.
OUTXCSR5 (DATA_ERR): The USB FCU sets this
bit to a “1” to indicate the reception of a CRC error or
a bit stuffing error in an ISO packet. The CPU writes a
“0” to clear this bit.
OUTXCSR6 (FLUSH): The CPU writes a “1” to flush
the OUT FIFO. If there is one packet in the OUT
FIFO, a flush will cause the OUT FIFO to be empty. If
there are two packets in the OUT FIFO, a flush will
cause the older packet to be flushed out from the
OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit dur-
ing reception could produce unpredictable results.
OUTXCSR7 (AUTO_CLR): If the CPU sets this bit to
a “1”, the OUT_PKT_RDY bit is cleared automatically
by the USB FCU after the number of bytes of data
equal to the maximum packet size (MAXP) is un-
loaded from the OUT FIFO (see section 1.21.3.2 for
details).
Fig. 1.65. USB Endpoint x OUT CSR (OUT_CSR)
OUTXCSR7
OUTXCSR5
OUTXCSR4
OUTXCSR3
OUTXCSR2
OUTXCSR1
OUTXCSR0
MSB
7
LSB
0
OUTXCSR6
Address: 005A
16
Access: R/W
Reset: 00
16
OUTXCSR0
OUT_PKT_RDY Flag (bit 0) (Write "0" onlyor Read)
0: Out packet is not ready
1: Out packet is ready
OUTXCSR1
OVER_RUN Flag (bit 1) (Write "0" only or Read)
0: No FIFO overrun
1: FIFO overrun occurred
OUTXCSR2
SEND_Stall Bit (bit 2)
0: No action
1: Stall OUT Endpoint X by the CPU
OUTXCSR3
ISO/TOGGLE_INIT Bit (bit 3)
0: Select non-isochronous transfer (0->1->0) reset data toggle to DATA0)
1: Select isochronous transfer
OUTXCSR4
FORCE_STALL Flag (bit 4) (Write "0" only or Read)
0: No action
1: Stall Endpoint X by the USB FCU
OUTXCSR5
DATA_ERR Flag (bit 5) (Write "0" only or Read)
0: No error
1: CRC or bit stuffing error received in an ISO packet
OUTXCSR6
FLUSH Bit (bit 6) (Write Only - Read "0")
0: No action
1: Flush the FIFO
OUTXCSR7
AUTO_CLR Bit (bit 7)
1: AUTO_CLR disabled
0: AUTO_CLR enabled
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