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| 型號： | M37640M8-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 23/96頁 |
| 文件大?。?/td> | 1477K |
| 代理商： | M37640M8-XXXFP |
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3
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.5 PIN DESCRIPTION AND LAYOUT
Table 1.1. Pin Description and Layout
NAME
I/O
DESCRIPTION
PIN #
P0
0/AB0~ P17/AB15
I/O
CMOS I/O port (address bus). When the MCU is in memory expansion or
microprocessor mode, these pins function as the address bus.
56-41
P2
0/DB0 ~ P27/DB7
I/O
CMOS I/O port (data bus). When the MCU is in memory expansion or microprocessor
mode, these pins function as the data bus. These pins may also be used to implement
the Key-on Wake up function.
64-57
P3
0/RDY
I/O
CMOS I/O port (Ready). When the MCU is in memory expansion or microprocessor
mode, this pin functions as RDY (hardware wait cycle control).
40
P3
1
I/O
CMOS I/O port.
39
P3
2
I/O
CMOS I/O port.
38
P3
3/DMA
out
I/O
CMOS I/O port (DMAout). When the MCU is in memory expansion or microprocessor
mode, this pin is set to a “1” during a DMA transfer.
37
P3
4/Φ
out
I/O
CMOS I/O port. When the MCU is in memory expansion or microprocessor mode,
this pin becomes
Φout pin.
36
P3
5/SYNC
out
I/O
CMOS I/O port (SYNCout). When the MCU is in memory expansion or
microprocessor mode, this pin becomes the SYNCout pin.
35
P3
6/WR
I/O
CMOS I/O port. (WR output). When the MCU is in memory expansion or microprocessor
mode, this pin becomes WR.
34
P37/RD
I/O
CMOS I/O port. (RD output). When the MCU is in memory expansion or microprocessor
mode, this pin becomes RD.
33
P4
0/EDMA
I/O
CMOS I/O port (EDMA: Expanded Data Memory Access). When the MCU is in memory
expansion or microprocessor mode, this pin can become the EDMA pin.
24
P4
1/INT0~ P42/INT1
I/O
CMOS I/O port or external interrupt ports INT0 and INT1. These external interrupts can
be configured to be active high or low.
23-22
P4
3/CNTR0
I/O
CMOS I/O port or Timer X input pin for pulse width measurement mode and event
counter mode or Timer X output pin for pulse output mode. This pin can also be used as
an external interrupt when Timer X is not in output mode. The interrupt polarity is
selected in the Timer X mode register.
21
P4
4/CNTR1
I/O
CMOS I/O port or Timer Y input pin for pulse period measurement mode, pulse H-L
measurement mode and event counter mode or Timer Y output pin for pulse output
mode. This pin can also be used as an external interrupt when Timer Y is not in output
mode. The interrupt polarity is selected in the Timer Y mode register.
20
P5
0/XC
in
I/O
CMOS I/O port or XCin.12
P5
1/Tout/XC
out
I/O
CMOS I/O port or Timer half pulse output pin (can be configured initially high or initially
low), or XCout.
11
P5
2/OBF0
I/O
CMOS I/O port or OBF
0 output to master CPU for data bus buffer 0.
8
P5
3/IBF0
I/O
CMOS I/O port or IBF
0 output to master CPU for data bus buffer 0.
7
P5
4/S0
I/O
CMOS I/O port or S
0 input from master CPU for data bus buffer 0.
6
P5
5/A0
I/O
CMOS I/O port or A
0 input from master CPU.
5
P5
6/R(E)
I/O
CMOS I/O port or R(E) input from master CPU.
4
P5
7/W(R/W)
I/O
CMOS I/O port or W(R/W) input from master CPU.
3
P6
0/DQ0~ P67/DQ7
I/O
CMOS I/O port or master CPU data bus.
2-1,
80-75
USB D-
I/O
USB D- voltage line interface, a series resistor of 33
should be connected to this pin.
71
USB D+
I/O
USB D+ voltage line interface, a series resistor of 33
should be connected to this pin.
70
P7
0/SOF
I/O
CMOS I/O port or USB start of frame pulse output, an 80 ns pulse outputs on this pin for
every USB frame.
69
P7
1/HOLD
I/O
CMOS I/O port or HOLD pin.
68
P7
2/S1
I/O
CMOS I/O port or S
1 input from master CPU for data bus buffer 1.
67
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