參數(shù)資料
型號: M37640M8-XXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 20/96頁
文件大?。?/td> 1477K
代理商: M37640M8-XXXFP
27
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.15.1 Interrupt Control
Each maskable interrupt has associated with it an in-
terrupt request bit and an interrupt enable bit. These
bits, along with the I flag, determine whether interrupt
events can cause an interrupt service request to be
generated. An interrupt request bit is set to “1” when
its corresponding interrupt event is activated. The bit is
cleared to a “0” when the interrupt is serviced or when
a “0” is written to the bit. The bit can not be set high
by writing “1” to it. Each interrupt enable bit deter-
mines whether the interrupt request bit it is paired with
is seen when the interrupts are polled. When the inter-
rupt enable bit is a “0”, the interrupt request bit is not
seen; and when the enable bit is a “1”, the interrupt re-
quest is seen.
The interrupt request registers (IREQ) for the 23
maskable interrupts are shown in Figure 1.24, Figure
1.25, and Figure 1.26. The interrupt control registers
(ICON) for the 23 maskable interrupts are shown in
Figure 1.27, Figure 1.28, and Figure 1.29.
Fig. 1.26. Interrupt Request Register C (IREQC)
Fig. 1.24. Interrupt Request Register A (IREQA)
Fig. 1.25.
Interrupt Request Register B (IREQB)
IRA5
IRA4
IRA2
IRA1
IRA0
MSB
7
LSB
0
IRA3
IRA7
IRA6
IRA 0
USB Function Interrupt Request (bit 0)
IRA 1
USB SOF Interrupt Request (bit 1)
IRA 2
External Interrupt 0 Request (bit 2)
IRA 3
External Interrupt 1 Request (bit 3)
IRA 4
DMAC channel 0 Interrupt Request (bit 4)
IRA 5
DMAC channel 1 Interrupt Request (bit 5)
IRA 6
UART1 Receive Buffer Full Interrupt Request (bit 6)
IRA 7
UART1 Transmit Interrupt Request (bit 7)
0: No interrupt request issued
1: Interrupt request issued
Address: 0002
16
Access:
R/W
Reset:
00
16
IRB5
IRB4
IRB2
IRB1
IRB0
MSB
7
LSB
0
IRB3
IRB7
IRB6
IRB 0
UART1 Error Sum Interrupt Request (bit 0)
IRB 1
UART2 Receive Buffer Full Interrupt Request (bit 1)
IRB 2
UART2 Transmit Interrupt Request (bit 2)
IRB 3
UART2 Error Sum Interrupt Request (bit 3)
IRB 4
Timer X Interrupt Request (bit 4)
IRB 5
Timer Y Interrupt Request (bit 5)
IRB 6
Timer 1 Interrupt Request (bit 6)
IRB 7
Timer 2 Interrupt Request (bit 7)
0: No interrupt request issued
1: Interrupt request issued
Address: 0003
16
Access:
R/W
Reset:
00
16
IRC5
IRC4
IRC2
IRC1
IRC0
MSB
LSB
0
IRC3
IRC6
IRC 0
Timer 3 Interrupt Request (bit 0)
IRC 1
External CNTR0 Interrupt Request (bit 1)
IRC 2
External CNTR1 Interrupt Request (bit 2)
IRC 3
SIO Interrupt Request (bit 3)
IRC 4
Input Buffer Full Interrupt Request (bit 4)
IRC 5
Output Buffer Empty Interrupt Request (bit 5)
IRC 6
Key-on Wake up Interrupt Request (bit 6)
0: No interrupt request issued
1: Interrupt request issued
Bit 7
Reserved (Read/Write “0”)
Address: 0004
16
Access:
R/W
Reset:
00
16
Reserved
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