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| 型號： | M37544 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 19/68頁 |
| 文件大小： | 579K |
| 代理商： | M37544 |
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7544 Group
Rev.1.04 2004.06.08 page 19 of 66
REJ03B0012-0104Z
Interrupts
Interrupts occur by 12 different sources : 5 external sources, 6 in-
ternal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by
the interrupt disable flag. When the interrupt enable bit and the in-
terrupt request bit are set to “1” and the interrupt disable flag is set
to “0”, an interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the
interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
[Interrupt edge selection register] INTEDGE
The valid edge of external interrupt INT
0
and INT
1
can be selected
by the interrupt edge selection bit, respectively.
By the key-on wakeup selection bit, enable/disable of a key-on
wakeup of P0
0
pin can be selected.
■
Notes on use
When setting the followings, the interrupt request bit may be set to
“1”.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A
16
)
Timer X mode register (address 2B
16
)
Timer A mode register (address 1D
16
)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit (active edge switch bit) to “1”.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
Table 6 Interrupt vector address and priority
Vector addresses (
Note 1
)
High-order
Priority
Low-order
Interrupt request generating conditions
Remarks
Interrupt source
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
Note 1:
Vector addressed contain internal jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
At reset input
At completion of serial I/O data receive
At completion of serial I/O transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT
0
input
At detection of either rising or falling edge of
INT
1
input
At falling of conjunction of input logical level
for port P0 (at input)
At detection of either rising or falling edge of
CNTR
0
input
At detection of either rising or falling edge of
CNTR
1
input
At timer X underflow
Not available
Not available
At timer A underflow
Not available
At completion of A/D conversion
At timer 1 underflow
Not available
At BRK instruction execution
1
2
3
4
5
6
7
8
9
—
—
10
—
11
12
—
13
Reset (
Note 2
)
Serial I/O receive
Serial I/O transmit
INT
0
INT
1
Key-on wake-up
CNTR
0
CNTR
1
Timer X
Reserved area
Reserved area
Timer A
Reserved area
A/D conversion
Timer 1
Reserved area
BRK instruction
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