參數(shù)資料
型號: M37517F8HP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 57/100頁
文件大小: 899K
代理商: M37517F8HP
Rev.1.01
Aug 02, 2004
page 4 of 96
7517 Group
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 7517 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
Fig. 3 Structure of CPU mode register
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
CPU mode register
(CPUM : address 003B16)
b7
b0
Stack page selection bit
0 : 0 page
1 : 1 page
Processor mode bits
b1 b0
0
0 : Single-chip mode
01 :
1
0 :
Not available
11 :
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillation function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
00 :
φ = f(XIN)/2 (high-speed mode)
01 :
φ = f(XIN)/8 (middle-speed mode)
1
0 :
φ = f(XCIN)/2 (low-speed mode)
1
1 : Not available
Clock source switch bit
0 : On-chip oscillation function
1 : XCIN–XCOUT oscillation function
Note : All bits in this register are protected by protect mode.
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