Rev.1.01
Aug 02, 2004
page 55 of 96
7517 Group
Fig. 63 State transitions of system clock
RESET
Clock
source
switch
bit
0
:
On-chip
oscillation
function
1
:
X
IN
-X
OUT
oscillation
function
CM
4
:
Port
Xc
switch
bit
0
:
I/O
port
function
(stop
oscillating)
1
:
X
CIN
-X
COUT
oscillating
function
CM
5
:
Main
clock(X
IN
-X
OUT
)stop
bit
0
:
oscillating
1
:
stopped
CM
7
,CM
6
:Main
clock
division
ratio
selection
bits
b7
b6
0
:
f=
f(X
IN
)/2
(high-speed
mode)
0
1
:
f=
f(X
IN
)/8
(middle-speed
mode)
1
0
:
f=
f(X
CIN
)/2
(low-speed
mode)
1
:
Not
available
CPU
mode
register
(003B
16
)
b7
CPUM
CM4
"1"
"0"
CM
4
"0"
"1"
CM
6
"1"
"0"
CM
4
"1"
"0"
CM
6
"1"
"0"
CM7
"1"
"0"
CM4
"1"
"0"
CM5
"1"
"0"
CM
6
"1"
"0"
CM
6
"1"
"0"
CM
7
"0"
"1"
CM
6
"1"
"0"
High-speed
on-chip
oscillation
stop
bit
0
:
oscillating
1
:
stopped
MISRG2
(0037
16
)
b2
CM4
"1"
"0"
CM
4
"0"
"1"
CM
6
"0"
"1"
CM
4
"1"
"0"
CM
6
"0"
"1"
CM7
"1"
"0"
CM4
"1"
"0"
MISGR2
(bit2)
"1"
"0"
CM
6
"1"
"0"
CM
6
"1"
"0"
CM
7
"1"
"0"
CM
6
"0"
"1"
CM
5
"1"
"0"
CM4
"1"
"0"
CM
5
"1"
"0"
CM4
"1"
"0"
CM
5
"0"
"1"
CM
5
"0"
"1"
MISRG2
(bit
2)
"1"
"0"
CM
3
"1"
"0"
X
IN
oscillation
high-speed
mode(f(
φ)=2MHz)
CM
7
=0
CM
6
=0
CM
5
=0(4MHz
oscillating)
CM
4
=0(32kHz
stopped)
CM
3
=1
MISRG2(bit2)=1(High-speed
on-chip
oscillating
stopped)
X
IN
oscillation
middle-speed
mode(f(
φ)=500kHz)
CM
7
=0
CM
6
=1
CM
5
=0(4MHz
oscillating)
CM
4
=1(32kHz
oscillating)
CM
3
=1
MISRG2(bit2)=1(High-speed
on-chip
oscillatin
stopped)
X
IN
oscillation
high-speed
mode(f(
φ)=2MHz)
CM
7
=0
CM
6
=0
CM
5
=0(4MHz
oscillating)
CM
4
=1(32kHz
oscillating)
CM
3
=1
MISRG2(bit2)=1(High-speed
on-chip
oscillating
stopped)
Low-speed
mode(f(
φ)=16kHz)
CM
7
=1
CM
6
=0
CM
5
=0(4MHz
oscillating)
CM
4
=1(32kHz
oscillating)
CM
3
=1
MISRG2(bit2)=1(High-speed
on-chip
oscillating
stopped)
On-chip
oscillation
high-speed
mode(f(
φ)=approximately
2MHz)
CM
7
=0
CM
6
=0
CM
5
=0(4MHz
oscillating)
CM
4
=1(32kHz
oscillating
)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
On-chip
oscillation
high-speed
mode(f(
φ)=approximately
2MHz)
CM
7
=0
CM
6
=0
CM
5
=1(4MHz
oscillating
stopped)
CM
4
=0(32kHz
stopped)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
b3
Notes
1
:
Switch
the
mode
by
the
allows
shown
between
the
mode
blocks.
(Do
not
switch
between
the
modes
directly
without
an
allow.)
2
:
The
all
modes
can
be
switched
to
the
stop
mode
or
the
wait
mode
and
return
to
the
source
mode
when
the
stop
mode
or
the
wait
mo
de
is
ended.
3
:
Timer
operates
in
the
wait
mode.
4
:
When
the
stop
mode
is
ended,
a
delay
of
approximately
2
ms
occurs
by
connecting
Timer
1
in
middle/high-speed
mode.
5
:
When
the
stop
mode
is
ended,
the
following
is
performed.
(1)
After
the
clock
is
restarted,
a
delay
of
approximately
16ms
occurs
in
low-speed
mode
if
Timer
12
count
source
selec
tion
bit
is
"0".
(2)
After
the
clock
is
restarted,
a
delay
of
approximately
250ms
occurs
in
low-speed
mode
if
Timer
12
count
source
selec
tion
bit
is
"1".
6
:
Wait
until
oscillation
stabilizes
after
oscillating
the
main
clock
X
IN
before
the
switching
from
the
low-speed
mode
to
middle/high-speed
mode.
7
:
The
example
assumes
that
4
MHz
is
being
applied
to
the
X
IN
pin
and
32
kHz
to
the
X
CIN
pin.
φindicates
the
internal
clock.
CM4
"1"
"0"
CM
3
"1"
"0"
MISRG2
(bit
2)
"1"
"0"
CM
3
"1"
"0"
Low-speed
mode(f(
φ)=16MHz)
CM
7
=1
CM
6
=0
CM
5
=1(4MHz
oscillating
stopped)
CM
4
=1(32kHz
oscillating)
CM
3
=1
MISRG2(bit2)=1(High-speed
on-chip
oscillating
stopped)
CM
3
"1"
"0"
MISRG2
(bit
2)
"1"
"0"
MISRG2
(bit
2)
"1"
"0"
Low-speed
mode(f(
φ)=16kHz)
CM
7
=1
CM
6
=0
CM
5
=1(4MHz
oscillating
stopped)
CM
4
=1(32kHz
oscillating)
CM
3
=0
MISRG2(bit2)=1(High-speed
on-chip
oscillating
stopped)
On-chip
oscillating
middle-speed
mode(f(
φ)=approximately
500kHz)
CM
7
=0
CM
6
=1
CM
5
=1(4MHz
oscillating
stopped)
CM
4
=1(32kHz
oscillating)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
Low-speed
mode(f(
φ)=16kHz)
CM
7
=1
CM
6
=0
CM
5
=1(4MHz
oscillating
stopped)
CM
4
=1(32kHz
oscillating)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
X
IN
oscillation
high-speed
mode(f(
φ)=2MHz)
CM
7
=0
CM
6
=0
CM
5
=0(4MHz
oscillating)
CM
4
=0(32kHz
stopped)
CM
3
=1
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
X
IN
oscillation
high-speed
mode(f(
φ)=2MHz)
CM
7
=0
CM
6
=0
CM
5
=0(4MHz
oscillating)
CM
4
=1(32kHz
oscillating
)
CM
3
=1
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
X
IN
oscillation
middle-speed
mode(f(
φ)=500
kHz)
CM
7
=0
CM
6
=1
CM
5
=0(4MHz
oscillating)
CM
4
=0(32kHz
stopped)
CM
3
=1
MISRG2(bit2)=1(High-speed
on-chip
oscillating
stopped)
X
IN
oscillation
middle-speed
mode(f(
φ)=500kHz)
CM
7
=0
CM
6
=1
CM
5
=0(4MHz
oscillating)
CM
4
=1(32kHz
oscillating)
CM
3
=1
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
On-chip
oscillating
middle-speed
mode(f(
φ)=approximately
500kHz)
CM
7
=0
CM
6
=1
CM
5
=0(4MHz
oscillating)
CM
4
=0(32kHz
stopped)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
On-chip
oscillating
middle-speed
mode(f(
φ)=approximately
500kHz)
CM
7
=0
CM
6
=1
CM
5
=0(4MHz
oscillating)
CM
4
=1(32kHz
oscillating)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
On-chip
oscillating
middle-speed
mode(f(
φ)=approximately
500kHz)
CM
7
=0
CM
6
=1
CM
5
=1(4MHz
oscillating
stopped)
CM
4
=0(32kHz
stopped)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
On-chip
oscillation
high-speed
mode(f(
φ)=approximately
2MHz)
CM
7
=0
CM
6
=0
CM
5
=1(4MHz
oscillating
stopped)
CM
4
=1(32kHz
oscillating
)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
X
IN
oscillation
middle-speed
mode(f(
φ)=500kHz)
CM
7
=0
CM
6
=1
CM
5
=0(4MHz
oscillating)
CM
4
=0(32kHz
stopped)
CM
3
=1
MISRG2(bit2)=0(High-speed
on-chip
oscillating)
On-chip
oscillation
high-speed
mode(f(
φ)=approximately
2MHz)
CM
7
=0
CM
6
=0
CM
5
=0(4MHz
oscillating)
CM
4
=0(32kHz
stopped)
CM
3
=0
MISRG2(bit2)=0(High-speed
on-chip
oscillating)