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| 型號： | M37281MFH-XXXSP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 44/172頁 |
| 文件大?。?/td> | 1319K |
| 代理商： | M37281MFH-XXXSP |
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M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Rev.1.01 2003.07.16 page 44 of 170
Fig. 8.6.12 Address Data Communication Format
S
Slave address
A
Data
A
Data
A/A
P
R/W
7 bits
“
0
”
1 to 8 bits
1 to 8 bits
S
Slave address
A
Data
A
Data
A
P
7 bits
“
1
”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address
1st 7 bits
A
A
Data
7 bits
“
0
”
8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
Slave address
2nd byte
A
Data
A/A
P
1 to 8 bits
S
Slave address
1st 7 bits
A
A
7 bits
“
0
”
8 bits
7 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
2nd byte
Data
1 to 8 bits
Sr
Slave address
1st 7 bits
A
Data
A
P
1 to 8 bits
“
1
”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
From master to slave
From slave to master
R/W
R/W
R/W
R/W
8.6.12 Precautions when using multi-master I
2
C-BUS interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as SEB,
CLB etc. is executed for each register of the multi-master I
2
C-BUS
interface are described below.
I
2
C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
I
2
C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
intended. It is because hardware changes the read/write bit (RBW)
at the above timing.
I
2
C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
I
2
C control register (S1D)
When the read-modify-write instruction is executed for this register
at detecting the START condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0–BC2) at the above timing.
I
2
C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure using multi-master
Procedure example (The necessary conditions of the generating
procedure are described as the following
to
).
—
LDA
SEI
BBS 5,S1,BUSBUSY
BUSFREE:
STA S0
LDM #$F0, S1
CLI
(Taking out of slave address value)
(Interrupt disabled)
(BB flag confirming and branch process)
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
BUSBUSY:
CLI
(Interrupt enabled)
Use “STA,” “STX” or “STY” of the zero page addressing instruction
for writing the slave address value to the I
2
C data shift register.
Use “LDM” instruction for setting trigger of START condition gener-
ating.
Write the slave address value of above
and set trigger of START
condition generating of above
continuously shown the above
procedure example.
Disable interrupts during the following three process steps:
BB flag confirming
Writing of slave address value
Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
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