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| 型號(hào)： | M37281MFH-XXXSP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁(yè)數(shù)： | 37/172頁(yè) |
| 文件大?。?/td> | 1319K |
| 代理商： | M37281MFH-XXXSP |
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Rev.1.01 2003.07.16 page 37 of 170
M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
8.6.4 I
2
C Control Register
The I
2
C control register (address 00F9
16
) controls the data commu-
nication format.
(1) Bits 0 to 2: Bit Counter (BC0
–
BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “000
2
” and
the address data is always transmitted and received in 8 bits.
(2) Bit 3: I
2
C Interface Use Enable Bit (ESO)
This bit enables usage of the multimaster I
2
C BUS interface. When
this bit is set to “0,” the use disable status is provided, so the SDA
and the SCL become high-impedance. When the bit is set to “1,” use
of the interface is enabled.
When ESO = “0,” the following is performed.
PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I
2
C
status register at address 00F8
16
).
Writing data to the I
2
C data shift register (address 00F6
16
) is dis-
abled.
(3) Bit 4: Data Format Selection Bit (ALS)
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
eral call (refer to “8.6.5 I
2
C Status Register,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
(4) Bit 5: Addressing Format Selection Bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
the high-order 7 bits (slave address) of the I
2
C address register (ad-
dress 00F7
16
) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected, all the bits of the I
2
C
address register are compared with address data.
(5) Bits 6 and 7:Connection Control Bits between I
2
C-BUS
Interface and Ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 8.6.5).
Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
Note:
When using multi-master I
2
C-BUS interface, set bits 3 and
4 of the serial I/O mode register (address 0213
16
) to “1.”
Moreover, set the corresponding direction register to “1” to
use the port as multi-master I
2
C-BUS interface.
“
0
”
“
1
”
BSEL0
SCL1/P1
1
SCL2/P1
2
“
0
”
“
1
”
BSEL1
“
0
”
“
1
”
BSEL0
SDA1/P1
3
SDA2/P1
4
“
0
”
“
1
”
BSEL1
Multi-master
I
2
C-BUS
interface
SCL
SDA
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