參數(shù)資料
型號(hào)： M37281MFH-XXXSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù)： 43/172頁(yè)
文件大?。?/td> 1319K
代理商： M37281MFH-XXXSP
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Rev.1.01 2003.07.16 page 43 of 170
M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
8.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
Set a slave address in the high-order 7 bits of the I
2
C address
register (address 00F7
16
) and “0” in the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “85
16
” in
the I
2
C clock control register (address 00FA
16
).
Set “10
16
” in the I
2
C status register (address 00F8
16
) and hold the
SCL at the HIGH.
Set a communication enable status by setting “48
16
” in the I
2
C
control register (address 00F9
16
).
Set the address data of the destination of transmission in the high-
order 7 bits of the I
2
C data shift register (address 00F6
16
) and set
“0” in the least significant bit.
Set “F0
16
” in the I
2
C status register (address 00F8
16
) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I
2
C data shift register (address 00F6
16
). At
this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step
.
Set “D0
16
” in the I
2
C status register (address 00F8
16
). After this, if
ACK is not returned or transmission ends, a STOP condition will
be generated.
8.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
Set a slave address in the high-order 7 bits of the I
2
C address
register (address 00F7
16
) and “0” in the RBW bit.
Set the no ACK clock mode and SCL = 400 kHz by setting “25
16
” in
the I
2
C clock control register (address 00FA
16
).
Set “10
16
” in the I
2
C status register (address 00F8
16
) and hold the
SCL at the HIGH.
Set a communication enable status by setting “48
16
” in the I
2
C
control register (address 00F9
16
).
When a START condition is received, an address comparison is
made.
When all transmitted address are“0” (general call):
AD0 of the I
2
C status register (address 00F8
16
) is set to “1”and
an interrupt request signal occurs.
When the transmitted addresses match the address set in
:
ASS of the I
2
C status register (address 00F8
16
) is set to “1” and
an interrupt request signal occurs.
In the cases other than the above:
AD0 and AAS of the I
2
C status register (address 00F8
16
) are set
to
“0” and no interrupt request signal occurs.
Set dummy data in the I
2
C data shift register (address 00F6
16
).
When receiving control data of more than 1 byte, repeat step
.
When a STOP condition is detected, the communication ends.
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