參數(shù)資料
型號(hào): M34571G6FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24
封裝: 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁(yè)數(shù): 40/126頁(yè)
文件大?。?/td> 1776K
代理商: M34571G6FP
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Rev.1.02
May 25, 2007
Page 20 of 124
REJ03B0179-0102
4571 Group
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt
enable bits (V10
V13, V20, V23), and interrupt request flag are
“1.The interrupt actually occurs 2 to 3 machine cycles after the
cycle in which all three conditions are satisfied. The interrupt
occurs after 3 machine cycles only when the three interrupt
conditions are satisfied on execution of other than one-cycle
instructions (Refer to Figure 22).
Fig 22. Interrupt sequence
T3
T2
T1
1 machine cycle
System clock
(STCK)
Interrupt enable
flag (INTE)
INT0
INT1
T1F
T2F
T3F
The program starts
from the interrupt
address.
Interrupt activated
condition is satisfied.
Flag cleared
2 to 3 machine cycles
(Notes 1, 2)
EXF0
EXF1
External 0,
External 1
interrupt
Timer 1
Timer 2
Timer 3
interrupt
VDF
Voltage drop
detection circuit
interrupt
When an interrupt request flag is set after its interrupt is enabled
EI instruction execution
cycle
Interrupt enabled state
Interrupt disabled state
Retaining level of system
clock for 4 periods or more
is necessary.
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time
when each interrupt activated condition is satisfied.
T3
T2
T1
T3
T2
T1
T3
T2
T1
T2
T1
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