參數(shù)資料
型號(hào)： M34571G6FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 14/126頁
文件大?。?/td> 1776K
代理商： M34571G6FP
Rev.1.02
May 25, 2007
Page 110 of 124
REJ03B0179-0102
4571 Group
Skip condition
C
a
rry
fl
ag
CY
Detailed description
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
V10 = 0 : (EXF0) = 1
When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request
flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)
(INT0) =
“L”
However, I12 = 0
When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L”. Executes the next instruction when
the level of INT0 pin is “H”.
(INT0) =
“H”
However, I12 = 1
When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H”. Executes the next instruction when
the level of INT0 pin is “L”. (I12: bit 2 of interrupt control register I1)
V11 = 0 : (EXF1) = 1
When V11 = 0 : Clears (0) to the EXF1 flag and skips the next instruction when external 1 interrupt request
flag EXF1 is “1”. When the EXF1 flag is “0”, executes the next instruction.
When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register
V1)
I22 = 0 :
(INT1) =
“L”
When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L”. Executes the next instruction when
the level of INT1 pin is “H”.
I22 = 1 :
(INT1) =
“H”
When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H”. Executes the next instruction when
the level of INT1 pin is “L”. (I22: bit 2 of interrupt control register I2)
Transfers the contents of interrupt control register V1 to register A.
Transfers the contents of register A to interrupt control register V1.
Transfers the contents of interrupt control register V2 to register A.
Transfers the contents of register A to interrupt control register V2.
Transfers the contents of interrupt control register I1 to register A.
Transfers the contents of register A to interrupt control register I1.
Transfers the contents of interrupt control register I2 to register A.
Transfers the contents of register A to interrupt control register I2.
Transfers the contents of register A (A1, A0) to timer control register PA.
Transfers the contents of timer control register W1 to register A.
Transfers the contents of register A to timer control register W1.
Transfers the contents of timer control register W2 to register A.
Transfers the contents of register A to timer control register W2.
Transfers the contents of timer control register W3 to register A.
Transfers the contents of register A to timer control register W3.
Transfers the contents of timer control register W5 to register A.
Transfers the contents of register A to timer control register W5.
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參數(shù)描述
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