參數(shù)資料
型號(hào)： M34571G6FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 115/126頁
文件大?。?/td> 1776K
代理商： M34571G6FP
Rev.1.02
May 25, 2007
Page 89 of 124
REJ03B0179-0102
4571 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB3
(Transfer data to Accumulator and register B from timer 3)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
0
111
00
10 2 27 2 16
11
-
Opera-
tion:
(B)
← (T37T34)
(A)
← (T33T30)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T37
T34) of timer 3 to reg-
ister B.
Transfers the low-order 4 bits (T33
T30) of timer 3 to regis-
ter A.
TABE
(Transfer data to Accumulator and register B from register E)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
0
010
10
10 2 02 A 16
11
-
Opera-
tion:
(B)
← (E7E4)
(A)
← (E3E0)
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E7
E4) of register E to reg-
ister B, and low-order 4 bits of register E to register A.
TABP p
(Transfer data to Accumulator and register B from Program memory in page p)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
00
10 p5 p4 p3 p2 p1 p0 2 0
8
+p
p 16
13
-
Opera-
tion:
(SP)
← (SP) + 1
(SK(SP))
← (PC)
(PCH)
← p
(PCL)
← (DR2DR0, A3A0)
(B)
← (ROM(PC))74
(A)
← (ROM(PC))30
(UPTF)
← 1
(DR1, DR0)
← (ROM(PC))9, 8
(DR2)
← 0
(PC)
← (SK(SP))
(SP)
← (SP) 1
Grouping:
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to
0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-
order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant
bit (DR2) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
Note:
M34571G4 : p = 0 to 31
M34571G6 : p = 0 to 47
M34571GD : p = 0 to 127
When this instruction is executed, be careful not to over the stack because 1
stage of stack register is used.
TABPS
(Transfer data to Accumulator and register B from Prescaler)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
0
111
01
01 2 27 5 16
11
-
Opera-
tion:
(B)
← (TPS7TPS4)
(A)
← (TPS3TPS0)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
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