參數(shù)資料
型號: M34570EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù): 61/69頁
文件大小: 687K
代理商: M34570EDFP
System Clock
65
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
System Clock
Clock Generation Circuit
Four circuits are incorporated to generate the system clock signal :
Main clock oscillation circuit
Sub clock oscillation circuit
Ring oscillator
PLL frequency synthesizer
Table 1.8.1 lists specifications of the clock generation circuit. Figure 1.8.1 shows a block diagram of the
clock generation circuit. Figures 1.8.2 to 1.8.8 show registers to control the clock.
CPU clock source
Peripheral function
clock source
Application
Main clock
generation circuit
Ring oscillator
PLL frequency
synthesizer
Sub clock
generation circuit
Item
CPU clock source
Timer A and B
clock source
CPU clock source
Peripheral function
clock source
CPU clock source
Peripheral function
clock source
Clock frequency
Up to 30 MHz
32.768 kHz
20 MHz, 30 MHz
Approximatly 1 MHz
Ceramic resonator
Crystal oscillator
Connectable or
additional circuit
oscillator
Crystal oscillator
Low pass filter
XIN, XOUT
Pins for oscillator
or for additional
circuit
XCIN, XCOUT
VCOUT (connect to
Low pass filter)
P86 (connect to Vss)
Available
Oscillation stop/
restart function
Oscillating
Oscillator status
after reset
Stopped
Externally
generated clock can
be input
Other
With PLL frequency
synthesizer, a sub
clock cannot be
used.
Externally
generated clock can
be input. With a sub
clock oscillation
circuit, PLL
frequency
synthesizer cannot
be used.
When main clock
oscillation stops, a ring
oscillator starts oscillating
automatically and
becomes a clock source
for CPU and peripheral
functions.
Available
Table 1.8.1. Clock Generation Circuit Specifications
相關PDF資料
PDF描述
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