參數(shù)資料
型號(hào)： M34570EDFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36
封裝： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁(yè)數(shù)： 10/69頁(yè)
文件大?。?/td> 687K
代理商： M34570EDFP
15
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(6) Interrupt control register
q Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are
assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1
instruction can be used to transfer the contents of register
V1 to register A.
Table 6 Interrupt control register
V13
V12
V11
V10
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
Interrupt control register V1
at reset : 00002
RAM back-up : 00002
R/W
V23
V22
V21
V20
Not used
Timer 3 interrupt enable bit
0
1
0
1
0
1
0
1
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
Interrupt control register V2
at reset : 00002
at RAM back-up : 00002
R/W
This bit has no function, but read/write is enabled.
Note: “R” represents read enabled, and “W” represents write enabled.
q Interrupt control register V2
Interrupt enable bit of timer 3 is assigned to register V2.
Set the contents of this register through register A with the
TV2A instruction. The TAV2 instruction can be used to
transfer the contents of register V2 to register A.
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參數(shù)描述
M34570M4 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
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