參數(shù)資料
型號: M34570EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù): 59/69頁
文件大?。?/td> 687K
代理商: M34570EDFP
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
63
Bus
_____
________
Figure 1.7.7. RD Signal Output Longer by RDY Signal
_________
(7) HOLD Signal
__________
The HOLD signal transfers a bus privileges from the CPU to external circuits. When setting the HOLD pin
to "L", the microcomputer becomes in a hold state after a bus access at the time is completed. The
__________
_________
microcomputer remains in a hold state while the HOLD pin is set to "L". The HLDA pin outputs "L". Table
1.7.7 shows a microcomputer state in a hold state.
__________
Bus is used in the following priority: HOLD, DMAC, CPU.
RDY received timing
(1) Separate bus (2 waits)
(2) Multiplex bus (2 waits)
BCLK
RD
CSi
(i=0 to 3)
RDY
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
1st cycle
2nd cycle
3rd cycle
4th cycle
tsu(RDY - BCLK)
RDY received timing
tsu(RDY-BCLK): RDY input setup time
RDY receive timing for i wait(s): j + 1st cycles (j = 1 to 3)
1st cycle
2nd cycle
3rd cycle
4th cycle
: Wait by RDY
: Wait by program
1
Note:
1. Chip-select (CSi) may be output ,longer depending on CPU status such as an instruction queue buffer.
Figure 1.7.8. Priority to Use Bus
__________
HOLD > DMAC > CPU
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