參數(shù)資料
型號: M34570EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù): 58/69頁
文件大?。?/td> 687K
代理商: M34570EDFP
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
62
Bus
(5) ALE Signal
The ALE signal latches an address of multiplex bus. An address should be latched at a falling edge of
ALE. The PM15 to PM14 bits in the PM1 register determine an output pin for the ALE signal.
ALE signal outputs to an internal space and external space.
Figure 1.7.6. ALE Signal and Address/data Bus
_______
(6) RDY Signal
_______
The RDY signal facilitates an access to external devices which need a longer access time. When setting
________
the RDY pin to "L" on the falling edge of last BCLK of bus cycle, a wait is inserted into the bus cycle. Then
________
when setting the RDY pin to "H" on the falling edge of the BCLK, the reset of bus cycle is resumed.
________
Table 1.7.6 lists a microcomputer state when the RDY signal inserts a wait into the bus cycle. Figure
_____
________
1.7.7 shows an example of the RD signal that is output longer by the RDY signal.
Table 1.7.6. Microcomputer Status in a Wait State1
Item
State
Oscillation
On
_____
RD signal, WR signal, address bus, data bus, CS
________
Maintains status when RDY signal is received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
On
Note:
________
1. The RDY signal cannot be received immediately before a software wait.
(1) 8-bit data bus
(2) 16-bit data bus
ALE
Address
Data
Address
D0/A0 to D7/A7
A8 to A15
ALE
Address
Data
Address
D0/A0 to D15/A15
A16 to A19
Note:
1. Data is placed in a high-impedance state when read.
2. With full space multiplex bus an address bus becomes I/O port.
Address
Address or CS
A16 to A19
1
2
A20/CS3
A21/CS2
A22/CS1
A23/CS0
A20/CS3
A21/CS2
A22/CS1
A23/CS0
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