8: REGISTERS
1-94
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
bit 7
GPO Control
This bit is used to control the state of the SUSPEND# when it is congured as GPO. The
SUSPEND# pin can be used as a power-down input (SUSPEND#) or as an output (GPO)
possibly used for controlling the LCD backlight power:
When MD9 = 0 at rising edge of RESET#, SUSPEND#/GPO is an active-low Schmitt
input used to put the S1D13505 into suspend mode – see “Power Save Modes” for
details.
When MD[10:9] = 01 at rising edge of RESET#, SUSPEND#/GPO is an output with a
reset state of 0.
When MD[10:9] = 11 at rising edge of RESET#, SUSPEND#/GPO is an output with a
reset state of 1.
When this bit = 1 the GPO output is set to the reset state.
When this bit = 0 the GPO output pin is set to the inverse of the reset state.
Note:
Changing this register to non-zero value, or to a different non-zero value, should be done
only when there are no read/write DRAM cycles. This condition occurs when all of the fol-
lowing are true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half Frame
Buffer is disabled (REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 =
00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0)
have remained 0 since chip reset. For further programming information, see
“S1D13505
Programming Notes and Examples
”, document number X23A-G-003-05.
bit 7
Reserved
bits 6–5
RC Timing Value (NRC) Bits [1:0]
These bits select the DRAM random-cycle timing parameter, tRC. These bits specify the
number (NRC) of MCLK periods (TM) used to create tRC. NRC should be chosen to meet
tRC as well as tRAS, the RAS pulse width. Use the following two formulae to calculate
NRC then choose the larger value. Note, these formulae assume an MCLK duty cycle of
50 +/- 5%.
NRC = Round-Up (tRC/TM)
NRC = Round-Up (tRAS/TM + NRP)if NRP = 1 or 2
= Round-Up (tRAS/TM + 1.55)if NRP = 1.5
The resulting tRC is related to NRC as follows:
tRC = (NRC) TM
GPIO Status / Control Register 1
REG[21h]
RW
GPO
Control
n/a
Performance Enhancement Register 0
REG[22h]
RW
Reserved
RC Timing
Value Bit 1
RC Timing
Value Bit 0
RAS#-to-
CAS# Delay
Value
RAS# Pre-
charge Timing
Value Bit 1
RAS# Pre-
charge Timing
Value Bit 0
Reserved