參數(shù)資料
型號: M34552G8FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù): 141/143頁
文件大?。?/td> 0K
代理商: M34552G8FP
8: REGISTERS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-85
SPECIFICATION (X23A-A-001-12)
bit 7
VRTC Polarity Select
This bit selects the polarity of the VRTC pulse to the CRT.
When this bit = 1, the VRTC pulse is active high.
When this bit = 0, the VRTC pulse is active low.
bit 6
FPFRAME Polarity Select
This bit selects the polarity of the FPFRAME pulse to the TFT/D-TFD or passive LCD.
When this bit = 1, the FPFRAME pulse is active high for TFT/D-TFD and active low for passive.
When this bit = 0, the FPFRAME pulse is active low for TFT/D-TFD and active high for passive.
bits 2–0
VRTC/FPFRAME Pulse Width Bits [2:0]
For CRT and TFT/D-TFD, these bits specify the pulse width of VRTC and FPFRAME
respectively. For passive LCD, FPFRAME is automatically created and these bits have no
effect.
VRTC/FPFRAME pulse width (lines) = VRTC/FPFRAME Pulse Width Bits [2:0] + 1
Note: This register must be programmed such that
(REG[0Ah] bits [5:0] + 1)
≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
VRTC/FPFRAME Pulse Width Register
REG[0Ch]
RW
VRTC Polar-
ity Select
FPFRAME
Polarity Select
n/a
VRTC/
FPFRAME
Pulse Width
Bit 2
VRTC/
FPFRAME
Pulse Width
Bit 1
VRTC/
FPFRAME
Pulse Width
Bit 0
Table 8-5 FPFRAME Polarity Selection
FPFRAME Polarity Select
Passive LCD FPFRAME Polarity TFT/D-TFD FPFRAME Polarity
0
active high
active low
1
active low
active high
相關(guān)PDF資料
PDF描述
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