參數(shù)資料
型號： M34552G8FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù)： 143/143頁
文件大?。?/td> 0K
代理商： M34552G8FP
8: REGISTERS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-87
SPECIFICATION (X23A-A-001-12)
bits 4–2
Bit-Per-Pixel Select Bits [2:0]
These bits select the color depth (bpp) for the displayed data. See Section 10.1, “Display
Mode Data Format” for details of how the pixels are mapped into the image buffer.
bit 1
CRT Enable
This bit enables the CRT monitor.
When this bit = 1, the CRT is enabled.
When this bit = 0, the CRT is disabled.
bit 0
LCD Enable
This bit enables the LCD panel.
Programming this bit from a 0 to a 1 starts the LCD power-on sequence.
Programming this bit from a 1 to a 0 starts the LCD power-off sequence.
REG[0Eh] bits 7–0
Screen 1 Line Compare Bits [9:0]
REG[0Fh] bits 1–0
These bits are set to 1 during power-on.
The display can be split into two images: Screen 1 and Screen 2, with Screen 1 above
Screen 2. This 10-bit value specifies the height of Screen 1.
Height of Screen 1 (lines) = Screen 1 Line Compare Bits [9:0] + 1
If the height of Screen 1 is less than the display height then the remainder of the display is
taken up by Screen 2. For normal operation (no split screen) this register must be set
greater than the Vertical Display Height register (e.g. set to the reset value of 3FFh).
See Section 10, “Display Conguration” for details.
Table 8-7 Bits-Per-Pixel Selection
Bit-per-pixel Select Bits [2:0]
Color Depth (bpp)
000
1 bpp
001
2 bpp
010
4 bpp
011
8 bpp
100
15 bpp
101
16 bpp
110
– 111
Reserved
Screen 1 Line Compare Register 0
REG[0Eh]
RW
Screen 1 Line
Compare Bit 7
Screen 1 Line
Compare Bit 6
Screen 1 Line
Compare Bit 5
Screen 1 Line
Compare Bit 4
Screen 1 Line
Compare Bit 3
Screen 1 Line
Compare Bit 2
Screen 1 Line
Compare Bit 1
Screen 1 Line
Compare Bit 0
Screen 1 Line Compare Register 1
REG[0Fh]
RW
n/a
Screen 1 Line
Compare Bit 9
Screen 1 Line
Compare Bit 8
Screen 1 Display Start Address Register 0
REG[10h]
RW
Start Address
Bit 7
Start Address
Bit 6
Start Address
Bit 5
Start Address
Bit 4
Start Address
Bit 3
Start Address
Bit 2
Start Address
Bit 1
Start Address
Bit 0
Screen 1 Display Start Address Register 1
REG[11h]
RW
Start Address
Bit 15
Start Address
Bit 14
Start Address
Bit 13
Start Address
Bit 12
Start Address
Bit 11
Start Address
Bit 10
Start Address
Bit 9
Start Address
Bit 8
Screen 1 Display Start Address Register 2
REG[12h]
RW
n/a
Start Address
Bit 19
Start Address
Bit 18
Start Address
Bit 17
Start Address
Bit 16
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