參數(shù)資料
型號(hào)： M34552G8FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁(yè)數(shù)： 3/143頁(yè)
文件大?。?/td> 0K
代理商： M34552G8FP
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8: REGISTERS
1-88
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
REG[10h] bits 7–0
Screen 1 Start Address Bits [19:0]
REG[11h] bits 7–0
These registers form the 20-bit address for the starting word of the Screen
1 image in the display buffer.
REG[12h] bits 3–0
Note that this is a word address. A combination of this register and the Pixel Panning reg-
ister (REG[18h]) can be used to uniquely identify the start (top left) pixel within the
Screen 1 image stored in the display buffer.
See Section 10, “Display Conguration” for details.
REG[13h] bits 7–0
Screen 2 Start Address Bits [19:0]
REG[14h] bits 7–0
These registers form the 20-bit address for the starting word of the Screen
2 image in the display buffer.
REG[15h] bits 3–0
Note that this is a word address.
A combination of this register and the Pixel Panning register (REG[18h]) can be used to
uniquely identify the start (top left) pixel within the Screen 2 image stored in the display
buffer.
See Section 10, “Display Conguration” for details.
REG[16h] bits 7–0
Memory Address Offset Bits [10:0]
REG[17h] bits 2–0
These bits form the 11-bit address offset from the starting word of line n to
the starting word of line n+1. This value is applied to both Screen 1 and
Screen 2.
Note that this value is in words.
A virtual image can be formed by setting this register to a value greater than the width of
the display. The displayed image is a window into the larger virtual image.
See Section 10, “Display Conguration” for details.
Screen 2 Display Start Address Register 0
REG[13h]
RW
Start Address
Bit 7
Start Address
Bit 6
Start Address
Bit 5
Start Address
Bit 4
Start Address
Bit 3
Start Address
Bit 2
Start Address
Bit 1
Start Address
Bit 0
Screen 2 Display Start Address Register 1
REG[14h]
RW
Start Address
Bit 15
Start Address
Bit 14
Start Address
Bit 13
Start Address
Bit 12
Start Address
Bit 11
Start Address
Bit 10
Start Address
Bit 9
Start Address
Bit 8
Screen 2 Display Start Address Register 2
REG[15h]
RW
n/a
Start Address
Bit 19
Start Address
Bit 18
Start Address
Bit 17
Start Address
Bit 16
Memory Address Offset Register 0
REG[16h]
RW
Memory
Address
Offset Bit 7
Memory
Address
Offset Bit 6
Memory
Address
Offset Bit 5
Memory
Address
Offset Bit 4
Memory
Address
Offset Bit 3
Memory
Address
Offset Bit 2
Memory
Address
Offset Bit 1
Memory
Address
Offset Bit 0
Memory Address Offset Register 1
REG[17h]
RW
n/a
Memory
Address
Offset Bit 10
Memory
Address
Offset Bit 9
Memory
Address
Offset Bit 8
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