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參數(shù)資料
| 型號： | M312L1713ETS-CAA |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 336K |
| 代理商： | M312L1713ETS-CAA |
DDR SDRAM
128MB, 256MB Registered DIMM
Rev. 1.2 August. 2003
Parameter
Symbol
AA
(DDR266@CL=2.0)
A2
(DDR266@CL=2.0)
B0
(DDR266@CL=2.5))
Unit
Note
Min
Max
Min
Max
Min
Max
Mode register set cycle time
tMRD
15
ns
DQ & DM setup time to DQS
tDS
0.5
ns
j, k
DQ & DM hold time to DQS
tDH
0.5
ns
j, k
Control & Address input pulse width
tIPW
2.2
ns
8
DQ & DM input pulse width
tDIPW
1.75
ns
8
Power down exit time
tPDEX
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
ns
Exit self refresh to read command
tXSRD
200
tCK
Refresh interval time
tREFI
15.6
us
4
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-ns
11
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-ns
10, 11
Data hold skew factor
tQHS
0.75
ns
11
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
2
Active to Read with Auto precharge
command
tRAP
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
13
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR266 & DDR200 devices to ensure proper sys-
tem performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
AC CHARACTERISTICS
DDR266
DDR200
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
Units
Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
TBD
0.5
4.0
V/ns
a, m
Input Slew Rate
tIS
tIH
Units
Notes
0.5 V/ns
0
ps
i
0.4 V/ns
+50
0
ps
i
0.3 V/ns
+100
0
ps
i
Input Slew Rate
tDS
tDH
Units
Notes
0.5 V/ns
0
ps
k
0.4 V/ns
+75
ps
k
0.3 V/ns
+150
ps
k
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