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參數(shù)資料
| 型號： | M312L1713ETS-CAA |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 336K |
| 代理商： | M312L1713ETS-CAA |
DDR SDRAM
128MB, 256MB Registered DIMM
Rev. 1.2 August. 2003
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Ordering Information
Operating Frequencies
Part Number
Density
Organization
Component Composition
Interface
M383L1713ETS-C(L)AA/A2/B0/A0
128MB
16M x 72
16Mx8( K4H280838E) * 9EA
SSTL_2
M383L3313ETS-C(L)AA/A2/B0/A0
256MB
32M x 72
16Mx8( K4H280838E) * 18EA
SSTL_2
M383L3310ETS-C(L)AA/A2/B0/A0
256MB
32M x 72
32Mx4( K4H280438E) * 18EA
SSTL_2
M312L1713ETS-C(L)AA/A2/B0/A0
128MB
16M x 72
16Mx8( K4H280838E) * 9EA
SSTL_2
M312L3313ETS-C(L)AA/A2/B0/A0
256MB
32M x 72
16Mx8( K4H280838E) * 18EA
SSTL_2
M312L3310ETS-C(L)AA/A2/B0/A0
256MB
32M x 72
32Mx4( K4H280438E) * 18EA
SSTL_2
AA(DDR266@CL=2)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
Speed @CL2
133MHz
100MHz
Speed @CL2.5
133MHz
-
CL-tRCD-tRP
2-2-2
2-3-3
2.5-3-3
2-2-2
Feature
Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2, 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
Serial presence detect with EEPROM
1,700mil / 1,200mil height & double sided
184Pin Registered DIMM based on 128Mb E-die (x4, x8)
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