參數(shù)資料
型號： M30LW128D110ZE6T
廠商： 意法半導(dǎo)體
英文描述： 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product
中文描述： 128兆位（兩個64兆比特，x8/x16，統(tǒng)一座，快閃記憶體）3V電源，多記憶體產(chǎn)品
文件頁數(shù)： 20/57頁
文件大?。?/td> 860K
代理商： M30LW128D110ZE6T
M30LW128D
20/57
must be written with A23 Low and the second two
with A23 High.
I
The first bus cycle sets up the Configure STS
command. A23 must be Low.
I
The second Bus Write cycle specifies one of the
four possible configurations, A23 must be Low,
(refer to Table 6, Configuration Codes):
– Ready/Busy mode
– Pulse on Erase complete mode
– Pulse on Program complete mode
– Pulse on Erase or Program complete mode
I
The third Bus Write cycle re-sets up the
Configure STS command. This time A23 must
be High.
I
The fourth re-specifies the configuration code
given in the second Bus Write cycle. A23 must
be High.
The device will not accept the Configure STS com-
mand while the Program/Erase controller is busy
or during Program/Erase Suspend. When STS pin
is pulsing it remains Low for a typical time of
250ns. Any invalid Configuration Code will set an
error in the Status Register.
The Configure STS command is not available with
the LFBGA88 package.
Table 5. Commands
Note: 1.
X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program
Address, PD Program Data, QA Query Address, QD Query Data, BA Any address in Block, PRA Protection register address, PRD
Protection Register Data, CC Configuration Code. The shaded areas highlight the differences with a single M58LW064D memory.
2. For Identifier addresses and data refer to Table 7, Read Electronic Signature.
3. For Query Address and Data refer to Appendix B, CFI.
4. Not available with LFBGA88 package.
Command
C
Bus Operations
1st Cycle
2nd Cycle
Subsequent
Final
Op.
Addr.
Data
Op.
Addr.
Data
Op.
Addr.
Data
Op.
Addr.
Data
Read Memory
Array
2
Write
RA
FFh Read
RA
RD
Read Electronic
Signature
≥
2
Write
X
90h Read
IDA
(2)
IDD
(2)
Read Status
Register
2
Write
PA/BA
70h Read
PA/BA
SRD
Read Query
≥
2
Write
X
98h Read
QA
(3)
QD
(3)
Clear Status
Register
1
Write
PA/BA
50h
Block Erase
2
Write
BA
20h Write
BA
D0
Word/Byte Program
2
Write
PA
40h
10h
Write
PA
PD
Write to Buffer and
Program
4+N Write
BA
E8h Write
BA
N
Write
PA
PD
Write
BA
D0h
Program/Erase
Suspend
1
Write
PA/BA
B0h
Program/Erase
Resume
1
Write
PA/BA
D0h
Block Protect
2
Write
BA
60h Write
BA
01h
Blocks Unprotect
4
Write 000000h 60h Write 000000h
D0h
Write 400000h 60h Write 400000h D0h
Protection Register
Program
2
Write
PRA
C0h Write
PRA
PRD
Configure STS
command
(4)
4
Write 000000h B8h Write 000000h
CC
Write 400000h B8h Write 400000h
CC
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