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| 型號(hào)： | M30LW128D110ZE6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
| 中文描述： | 128兆位（兩個(gè)64兆比特，x8/x16，統(tǒng)一座，快閃記憶體）3V電源，多記憶體產(chǎn)品 |
| 文件頁數(shù)： | 12/57頁 |
| 文件大?。?/td> | 860K |
| 代理商： | M30LW128D110ZE6T |
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M30LW128D
12/57
MEMORY ENABLE
Each internal M58LW064D memory has 3 Chip
Enable signals to allow up to 4 memories to be
connected together without the use of additional
glue logic, see Table 2, Single M58LW064D De-
vice Enable. In this way the address space is con-
tiguous and the microcontroller only requires one
Chip Enable, E, to control both memories.
Figure 6 shows how a 128Mbit Stacked Flash
memory is created using two M58LW064D memo-
ries. One of the memories is located in the Upper
Address space and is referred to as the Upper
Memory, the other is located in the lower address
space and is referred to as the Lower Memory, see
Figure 7, Block Addresses.
The E0, E1 and E2 Chip Enables of each
M58LW064D memory are connected internally, as
shown in Figure 6.
The external signal A23 is used to select between
the Upper and Lower memories. A23 is connected
to E2 of the Upper Memory and to E1 of the Lower
Memory.
E1 of the Upper Memory is always connected to
V
DD
while E2 of the Lower Memory is always con-
nected to V
SS
.
The external Chip Enable, E, is used to enable or
disable the memory selected by A23, see Table 3,
M30LW128D Device Enable. E is connected to the
E0 signal of both memories.
The M30LW128D (TSOP56 and TBGA64 packag-
es only) supports both x8 and x16 bus widths. It is
also possible to have a x32 bus width by connect-
ing two x16 bus width M30LW128D devices to-
gether. Note that the two M30LW128D devices
must use the same E0 as Chip Enable, as E1 and
E2 are not connected internally.
Table 2. Single M58LW064D Device Enable, E2, E1 and E0
Table 3. M30LW128D Device Enable, A23 and E
Note: 1. UM = Upper Memory, LM = Lower Memory.
E2
E1
E0
Device
V
IL
V
IL
V
IL
Enabled
V
IL
V
IL
V
IH
Disabled
V
IL
V
IH
V
IL
Disabled
V
IL
V
IH
V
IH
Disabled
V
IH
V
IL
V
IL
Enabled
V
IH
V
IL
V
IH
Enabled
V
IH
V
IH
V
IL
Enabled
V
IH
V
IH
V
IH
Disabled
A23
Internal Signals
Chip Enable, E
Upper Memory
Lower Memory
E2
UM
= E1
LM
(1)
E1
UM
(1)
E2
LM
(1)
E0
UM
= E0
LM
(1)
V
IL
V
DD
(V
IH
)
V
SS
(V
IL
)
V
IL
Disabled
Enabled
V
IL
V
IH
Disabled
Disabled
V
IH
V
IL
Enabled
Disabled
V
IH
V
IH
Disabled
Disabled
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