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| 型號： | M30LW128D110ZE6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
| 中文描述： | 128兆位（兩個64兆比特，x8/x16，統(tǒng)一座，快閃記憶體）3V電源，多記憶體產(chǎn)品 |
| 文件頁數(shù)： | 10/57頁 |
| 文件大?。?/td> | 860K |
| 代理商： | M30LW128D110ZE6T |
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M30LW128D
10/57
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Input (A0).
The A0 address input is
used to select the higher or lower Byte in x8 mode.
It is not used in x16 mode (where A1 is the Lowest
Significant bit).
The A0 address input is not available with the
LFBGA88 package.
Address Inputs (A1-A22).
The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
The device must be enabled (refer to Table 3,
M30LW128D Device Enable) when selecting the
addresses. The address inputs are latched on the
rising edge of Write Enable or Chip Enable, E,
whichever occurs first.
Address Input (A23).
Address Input A23 is used
to select between the two internal memories.
When it is High, V
IH
, it selects the Upper Memory,
when it is Low, V
IL
, it selects the Lower Memory.
Refer to Memory Enable section for more details.
Data Inputs/Outputs (DQ0-DQ15).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, E, whichever
occurs first.
When the device is enabled and Output Enable is
low, V
IL
, the data bus outputs data from the mem-
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the device is deselected, Output En-
able is high, V
IH,
or the Reset/Power-Down signal
is low, V
IL
. When the Program/Erase Controller is
active the Ready/Busy status is given on DQ7.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. The M30LW128D
stacked memory uses the A23 address line and
the external Chip Enable, E, to select and enable
the internal memories. Refer to Memory Enable
section and Table 3, for more details.
When the Chip Enable deselects the memory,
power consumption is reduced to the Standby lev-
el, I
DD1
.
Output Enable (G).
The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at V
IH
the outputs are high impedance.
Write Enable (W).
The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able.
Reset/Power-Down (RP).
The
Down signal can be used to apply a Hardware Re-
set to the memory.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, V
IL
, for at least t
PLPH
. When
Reset/Power-Down is Low, V
IL
, the Status Regis-
ter information is cleared and the power consump-
tion is reduced to power-down level. The device is
deselected and outputs are high impedance. If Re-
set/Power-Down goes low, V
IL
,during a Block
Erase, a Write to Buffer and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the STS pin
stays low, V
IL
, for a maximum timing of t
PLPH
+ t
PH-
BH,
until the completion of the Reset/Power-Down
pulse.
After Reset/Power-Down goes High, V
IH
, the de-
vice will be ready for Bus Read and Bus Write op-
erations after t
PHQV
. Note that STS does not fall
during a reset, see Ready/Busy Output section.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the device is performing an
Erase or Program operation, the device may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
Byte/Word Organization Select (BYTE).
The
Byte/Word Organization Select signal is used to
switch between the x8 and x16 bus widths of the
memory. When Byte/Word Organization Select is
Low, V
IL
, the memory is in x8 mode, when it is
High, V
IH
, the memory is in x16 mode.
The Byte/Word Organization Select signal is not
available with the LFBGA88 package.
Status/(Ready/Busy) (STS).
The STS signal is
an open drain output that can be used to identify
the Program/Erase Controller status. It can be
configured in two modes:
I
Ready/Busy - the pin is Low, V
OL
, during
Program and Erase operations and high
impedance when the memory is ready for any
Read, Program or Erase operation.
Reset/Power-
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