參數(shù)資料
型號(hào): M30L0R7000T0ZAQT
廠商: 意法半導(dǎo)體
英文描述: CAP 0.22UF 50V 20% X7R DIP-2 BULK R-MIL-C-39014
中文描述: 128兆位(8兆x16插槽,多銀行,多層次,多突發(fā)),1.8V電源快閃記憶體
文件頁(yè)數(shù): 7/83頁(yè)
文件大?。?/td> 1329K
代理商: M30L0R7000T0ZAQT
7/83
M30L0R7000T0, M30L0R7000B0
Figure 2. Logic Diagram
Table 1. Signal Names
AI08337
23
A0-A22
W
DQ0-DQ15
VDD
M30L0R7000T0
M30L0R7000TB
E
VSS
16
G
RP
WP
VDDQVPP
L
K
WAIT
VSSQ
A0-A22
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command
Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset
WP
Write Protect
K
Clock
L
Latch Enable
WAIT
Wait
V
DD
Supply Voltage
V
DDQ
Supply Voltage for Input/Output
Buffers
V
PP
Optional Supply Voltage for
Fast Program & Erase
V
SS
Ground
V
SSQ
Ground Input/Output Supply
NC
Not Connected Internally
DU
Do Not Use
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