參數(shù)資料
型號(hào)： M30L0R7000T0ZAQT
廠商： 意法半導(dǎo)體
英文描述： CAP 0.22UF 50V 20% X7R DIP-2 BULK R-MIL-C-39014
中文描述： 128兆位（8兆x16插槽，多銀行，多層次，多突發(fā)），1.8V電源快閃記憶體
文件頁(yè)數(shù)： 12/83頁(yè)
文件大小： 1329K
代理商： M30L0R7000T0ZAQT
M30L0R7000T0, M30L0R7000B0
12/83
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the program and erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time to monitor
the progress or the result of the operation.
The Command Interface is reset to read mode
when power is first applied, when exiting from Re-
set or whenever V
DD
is lower than V
LKO
. Com-
mand sequences must be followed exactly. Any
invalid combination of commands will be ignored.
Refer to
Table 4., Command Codes
,
Table
5., Standard Commands
, and
Table 6., Factory
Program Command
, for a summary of the Com-
mand Interface.
Table 4. Command Codes
Read Array Command
The Read Array command returns the addressed
bank to Read Array mode.
One Bus Write cycle is required to issue the Read
Array command. Once a bank is in Read Array
mode, subsequent read operations will output the
data from the memory array.
A Read Array command can be issued to any
banks while programming or erasing in another
bank.
If the Read Array command is issued to a bank
currently executing a program or erase operation,
the bank will return to Read Array mode but the
program or erase operation will continue, however
the data output from the bank is not guaranteed
until the program or erase operation has finished.
The read modes of other banks are not affected.
Read Status Register Command
The device contains a Status Register that is used
to monitor program or erase operations.
The Read Status Register command is used to
read the contents of the Status Register for the ad-
dressed bank.
One Bus Write cycle is required to issue the Read
Status Register command. Once a bank is in Read
Status Register mode, subsequent read opera-
tions will output the contents of the Status Regis-
ter.
The Status Register data is latched on the falling
edge of the Chip Enable or Output Enable signals.
Either Chip Enable or Output Enable must be tog-
gled to update the Status Register data
The Read Status Register command can be is-
sued at any time, even during program or erase
operations. The Read Status Register command
will only change the read mode of the addressed
bank. The read modes of other banks are not af-
fected. Only Asynchronous Read and Single Syn-
chronous Read operations should be used to read
the Status Register. A Read Array command is re-
quired to return the bank to Read Array mode.
See
Table 9.
for the description of the Status Reg-
ister Bits.
Read Electronic Signature Command
The Read Electronic Signature command is used
to read the Manufacturer and Device Codes, the
Lock Status of the addressed bank, the Protection
Register, and the Configuration Register.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once a bank is in
Read Electronic Signature mode, subsequent
read operations in the same bank will output the
Manufacturer Code, the Device Code, the Lock
Hex Code
Command
01h
Block Lock Confirm
03h
Set Configuration Register Confirm
10h
Alternative Program Setup
20h
Block Erase Setup
2Fh
Block Lock-Down Confirm
40h
Program Setup
50h
Clear Status Register
60h
Block Lock Setup, Block Unlock Setup,
Block Lock Down Setup and Set
Configuration Register Setup
70h
Read Status Register
80h
Buffer Enhanced Factory Program
90h
Read Electronic Signature
98h
Read CFI Query
B0h
Program/Erase Suspend
C0h
Protection Register Program
D0h
Program/Erase Resume, Block Erase
Confirm, Block Unlock Confirm or Buffer
Program Confirm
E8h
Buffer Program
FFh
Read Array
相關(guān)PDF資料
PDF描述
M30L0R7000B0ZAQT CAP 0.047UF 100V 20% X7R DIP-2 BULK R-MIL-C-39014
M30L0R8000T0ZAQ 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0ZAQF 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0ZAQT 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0ZAQE AB 35C 7#12,28#16 PIN RECP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30L0R7000XX 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
M30L0R8000B0 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQ 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQE 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQF 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*