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參數(shù)資料
| 型號： | M30L0R7000T0ZAQT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP 0.22UF 50V 20% X7R DIP-2 BULK R-MIL-C-39014 |
| 中文描述： | 128兆位（8兆x16插槽，多銀行，多層次，多突發(fā)），1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 6/83頁 |
| 文件大小： | 1329K |
| 代理商： | M30L0R7000T0ZAQT |
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M30L0R7000T0, M30L0R7000B0
6/83
SUMMARY DESCRIPTION
The M30L0R7000T0/B0 is a 128 Mbit (8Mbit x16)
non-volatile Flash memory that may be erased
electrically at block level and programmed in-sys-
tem on a Word-by-Word basis using a 1.7V to 2.0V
V
DD
supply for the circuitry and a 1.7V to 2.0V
V
DDQ
supply for the Input/Output pins. An optional
9V V
PP
power supply is provided to speed up fac-
tory programming.
The device features an asymmetrical block archi-
tecture and is based on a multi-level cell technolo-
gy. M30L0R7000T0/B0 has an array of 131
blocks, and is divided into 8 Mbit banks. There are
15 banks each containing 8 main blocks of 64
KWords, and one parameter bank containing 4 pa-
rameter blocks of 16 KWords and 7 main blocks of
64 KWords. The Multiple Bank Architecture allows
Dual Operations, while programming or erasing in
one bank, read operations are possible in other
banks. Only one bank at a time is allowed to be in
program or erase mode. It is possible to perform
burst reads that cross bank boundaries. The bank
architecture is summarized in
Table 2.
, and the
memory maps are shown in
Figure 4.
The Param-
eter Blocks are located at the top of the memory
address space for the M30L0R7000T0, and at the
bottom for the M30L0R7000B0.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage V
DD
. There is a Buffer Enhanced Factory
programming command available to speed up pro-
gramming.
Program and erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The device supports Synchronous Burst Read and
Asynchronous Read from all blocks of the memory
array; at power-up the device is configured for
Asynchronous Read. In Synchronous Burst Read
mode, data is output on each clock cycle at fre-
quencies of up to 54MHz. The Synchronous Burst
Read operation can be suspended and resumed.
The device features an Automatic Standby mode.
When the bus is inactive during Asynchronous
Read operations, the device automatically switch-
es to the Automatic Standby mode. In this condi-
tion the power consumption is reduced to the
standby value and the outputs are still driven.
The M30L0R7000T0/B0 features an instant, indi-
vidual block locking scheme that allows any block
to be locked or unlocked with no latency, enabling
instant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
PP
≤
V
PPLK
all blocks are protected against
program or erase. All blocks are locked at power-
up.
The device includes 17 Protection Registers and 2
Protection Register locks, one for the first Protec-
tion Register and the other for the 16 One-Time-
Programmable (OTP) Protection Registers of 128
bits each. The first Protection Register is divided
into two segments: a 64 bit segment containing a
unique device number written by ST, and a 64 bit
segment One-Time-Programmable (OTP) by the
user. The user programmable segment can be
permanently protected.
Figure 5.
, shows the Pro-
tection Register Memory Map.
The memory is available in a TFBGA88,
8 x 10mm, 0.8mm pitch package.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The memory is supplied with all the bits erased
(set to ’1’).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30L0R7000B0ZAQT | CAP 0.047UF 100V 20% X7R DIP-2 BULK R-MIL-C-39014 |
| M30L0R8000T0ZAQ | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQF | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQT | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30L0R7000XX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R8000B0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0ZAQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
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