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參數資料
| 型號： | M30L0R7000T0 |
| 廠商： | 意法半導體 |
| 英文描述： | 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| 中文描述： | 128兆位（8兆x16插槽，多銀行，多層次，多突發(fā)），1.8V電源快閃記憶體 |
| 文件頁數： | 11/83頁 |
| 文件大小： | 1329K |
| 代理商： | M30L0R7000T0 |
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11/83
M30L0R7000T0, M30L0R7000B0
should be as close as possible to the pack-
age). See
Figure 9., AC Measurement Load Cir-
cuit
. The PCB trace widths should be sufficient
to carry the required V
PP
program and erase
currents.
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Ad-
dress Latch, Output Disable, Standby and Reset.
See
Table 3., Bus Operations
, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read.
Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at V
IL
in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
See Figures
10
,
11
,
12
and
13
Read AC Wave-
forms, and Tables
21
and
22
Read AC Character-
istics, for details of when the output becomes
valid.
Bus Write.
Bus Write operations write Com-
mands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at V
IL
with
Output Enable at V
IH
. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
the Latch Enable should be tied to V
IH
during the
bus write operation.
See Figures
16
and
17
, Write AC Waveforms, and
Tables
23
and
24
, Write AC Characteristics, for
details of the timing requirements.
Address Latch.
Address latch operations input
valid addresses. Both Chip enable and Latch En-
able must be at V
IL
during address latch opera-
tions. The addresses are latched on the rising
edge of Latch Enable.
Output Disable.
The outputs are high imped-
ance when the Output Enable is at V
IH
.
Standby.
Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in standby when
Chip Enable and Reset are at V
IH
. The power con-
sumption is reduced to the standby level I
DD4
and
the outputs are set to high impedance, indepen-
dently from the Output Enable or Write Enable in-
puts. If Chip Enable switches to V
IH
during a
program or erase operation, the device enters
Standby mode when finished.
Reset.
During Reset mode the memory is dese-
lected and the outputs are high impedance. The
memory is in Reset mode when Reset is at V
IL
.
The power consumption is reduced to the Standby
level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to
V
SS
during a Program or Erase, this operation is
aborted and the memory content is no longer valid.
Table 3. Bus Operations
Note: 1. X = Don't care.
2. L can be tied to V
IH
if the valid address has been previously latched.
3. Depends on G.
4. WAIT signal polarity is configured using the Set Configuration Register command.
Operation
E
G
W
L
RP
WAIT
(4)
DQ15-DQ0
Bus Read
V
IL
V
IL
V
IH
V
IL(2)
V
IH
Data Output
Bus Write
V
IL
V
IH
V
IL
V
IL(2)
V
IH
Data Input
Address Latch
V
IL
X
V
IH
V
IL
V
IH
Data Output or Hi-Z
(3)
Output Disable
V
IL
V
IH
V
IH
X
V
IH
Hi-Z
Hi-Z
Standby
V
IH
X
X
X
V
IH
Hi-Z
Hi-Z
Reset
X
X
X
X
V
IL
Hi-Z
Hi-Z
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| M30L0R7000T0ZAQ | 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000xx | 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000B0 | 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M30L0R7000T0ZAQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000XX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
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