deveopmen
DMAC
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
78
Item
Specification
No. of channels
Transfer memory space
4 (cycle steal method)
From any address in the 16 Mbytes space to a fixed address (16
Mbytes space)
From a fixed address (16 Mbytes space) to any address in the 1 M
bytes space
Maximum No. of bytes transferred
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
DMA request factors (Note)
Falling edge of INT0 to INT3 or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to UART4 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 is the first priority)
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
Single transfer
Transfer ends when the transfer count register is "0000
16
".
Repeat transfer
When the transfer counter is "0000
16
", the value in the transfer
counter reload register is reloaded into the transfer counter and the
DMA transfer is continued
DMA interrupt request generation timing
When the transfer counter register changes from "0001
16
" to "0000
16
".
DMA startup
Single transfer
Transfer starts when DMA transfer count register is more than
"0001
16
" and the DMA is requested after “01
2
” is written to the
channel i transfer mode select bits
Repeat transfer
Transfer starts when the DMA is requested after “11
2
” is written to the
channel i transfer mode select bits
DMA shutdown
Single transfer
When “00
2
” is written to the channel i transfer mode select bits and
DMA transfer count register becomes "0000
16
" by DMA transfer or
write
Repeat transfer
When “00
2
” is written to the channel i transfer mode select bits
Reload timing
When the transfer counter register changes from "0001
16
" to "0000
16
" in
repeat transfer mode.
Reading / writing the register
Registers are always read/write enabled.
Number of DMA transfer cycles
Between SFR and internal RAM : 3 cycles
Between external I/O and external memory : minimum 3 cycles
Table 1.11.1. DMAC specifications
Note: DMA transfer is not effective to any interrupt.