deveopmen
SFR
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
20
Figure 1.5.1. Location of peripheral unit control registers (1)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
0066
16
0067
16
0068
16
0069
16
006A
16
006B
16
006C
16
006D
16
006E
16
006F
16
0070
16
0071
16
0072
16
0073
16
0074
16
0075
16
0076
16
0077
16
0078
16
0079
16
007A
16
007B
16
007C
16
007D
16
007E
16
007F
16
0080
16
0081
16
0082
16
0083
16
0084
16
0085
16
0086
16
0087
16
0088
16
0089
16
008A
16
008B
16
008C
16
008D
16
008E
16
008F
16
0090
16
0091
16
0092
16
0093
16
0094
16
0095
16
0096
16
0097
16
0098
16
0099
16
009A
16
009B
16
009C
16
009D
16
009E
16
009F
16
00A0
16
00A1
16
00A2
16
00A3
16
00A4
16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Wait control register (WCR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
External data bus widthcontrol register (DS)
Main clock division register (MCD)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt register 2 (RMAD2)
Address match interrupt register 3 (RMAD3)
Emulator interrupt vector table register (EIAD)
Emulator interrupt detect register (EITD)
Emulator protect register (EPRR)
ROM areaset register (ROA)
Debug monitor area set register (DBA)
Expansion area set register 0 (EXA0)
Expansion area set register 1 (EXA1)
Expansion area set register 2 (EXA2)
Expansion area set register 3 (EXA3)
DRAM control register (DRAMCONT)
DRAM reflesh interval set register (REFCNT)
Timer A1 interrupt control register (TA1IC)
UART4 transmit/NACK interrupt control register (S4TIC)
UART0 transmit interrupt control register (S0TIC)
Bus collision detection(UART4) interrupt control register (BCN4IC)
Timer A0 interrupt control register (TA0IC)
UART3 receive/ACK interrupt control register (S3RIC)
Timer A2 interrupt control register (TA2IC)
UART4 receive/ACK interrupt control register (S4RIC)
UART0 receive interrupt control register (S0RIC)
A-D conversion interrupt control register (ADIC)
UART2 transmit/NACK interrupt control register (S2TIC)
DMA3 interrupt control register (DM3IC)
UART1 receive interrupt control register (S1RIC)
DMA2 interrupt control register (DM1IC)
UART2 receive/ACK interrupt control register (S2RIC)
DMA0 interrupt control register (DM0IC)
Timer B5 interrupt control register (TB5IC)
Key input interrupt control register (KUPIC)
Timer B0 interrupt control register (TB0IC)
Bus collision detection(UART3) interrupt control register (BCN3IC)
INT1 interrupt control register (INT1IC)
Timer B2 interrupt control register (TB2IC)
Timer A3 interrupt control register (TA3IC)
Bus collision detection(UART2) interrupt control register (BCN2IC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Exit priority register (RLVL)
Timer B1 interrupt control register (TB1IC)
Timer A4 interrupt control register (TA4IC)
INT3 interrupt control register (INT3IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
INT5 interrupt control register (INT5IC)
INT4 interrupt control register (INT4IC)
UART3 transmit/NACK interrupt control register (S3TIC)
UART1 transmit interrupt control register (S1TIC)
DMA1 interrupt control register (DM1IC)
*
*
*
*
*
*
*
As this register is used exclusively for debugger purposes, user cannot use this. Do not access to the register.
(The blank area is reserved and cannot be used by user.)