deveopmen
Power Saving
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
51
Figure 1.8.7. Clock transition
Wait mode
CPU operation stopped
CM10=“1”
Transition of stop mode, wait mode
BCLK :f(X
IN
)/8
CM07=“0” MCD=“08
16
”
Main clock is oscillating
Sub clock is oscillating
Main clock is oscillating
Sub clock is stopped
Note 1: Switch clocks after oscillation of main clock is fully stable.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: Set the desired division to the main clock division register (MCD).
Note 4: When shifting to division by 8 mode, MCD is set to "08
16
".
Main clock is oscillating
Sub clock is stopped
Medium-speed mode (divided-by-8 mode)
CM04=“1”
MCD=“XX
16
”
Note 1, 3
CM04=“0”
BCLK :f(X
IN
)
/division rate
CM07=“0” MCD=“XX
16
”
Note 4
BCLK :f(X
IN
)
CM07=“0” MCD=“12
16
”
High-speed mode
Medium-speed mode
(divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode)
BCLK :f(X
IN
)
/division rate
CM07=“0” MCD=“XX
16
”
Note 4
BCLK :f(X
IN
)
CM07=“0” MCD=“12
16
”
High-speed mode
Medium-speed mode
(divided-by-2, 3, 4, 6, 10, 12, 14 and 16 mode)
Transition of normal mode
Please change according to a direction of an arrow.
Normal mode
(Please see the following as transition of normal mode.)
CM10=“1”
Stop mode
All oscillators stopped
Wait mode
CPU operation stopped
CM04=“1”
CM05=“0”
Note 4
BCLK :f(X
CIN
)
CM07=“1”
Low-speed mode
BCLK :f(X
CIN
)
CM07=“1”
Main clock is oscillating
Sub clock is oscillating
MCD=“XX
16
”
Note 1, 3
CM07=“0
Note 1
MCD=“XX
16
”
Note 3
CM07=“1”
Note 2
CM10=“1”
Stop mode
All oscillators stopped
Wait mode
CPU operation stopped
CM07=“0”
Note 1
MCD=“XX
16
”
Note 3
CM04=“1”
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
Note 3
Interrupt
Interrupt
Low power
dissipation mode
CM05=“1”
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Medium-speed mode
(Divided-by-8 mode)
Note 1
Note 2
Note 1
Note 1: Switch clocks after oscillation of main clock is fully stable. After stop mode or when main clock oscillation is stopped,
transferred to the middle speed mode.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: The main ckock devision register is set to the division by 8 mode (MCD="08
16
").
Note 4: When shifting to low power dissipation mode, the main ckock devision register is set to the division by 8 mode (MCD="08
16
").
CM07=“1”
Note 2
CM05=“1”
High-speed/medium-speed mode
Low-speed/low power dissipation mode
Main clock is stopped
Sub clock is oscillating
Reset
Note 4