參數(shù)資料
型號(hào)： M306N0MCT-XXXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 64/158頁
文件大小： 3298K
代理商： M306N0MCT-XXXXFP
156
CPU Rewrite Mode
Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During erase/program mode, set BCLK to one of the following frequencies by changing the divide
ratio:
5 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
10 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)(Note 1)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable
interrupts may be used by setting the interrupt vector table in a location outside the flash memory
area.
Note 1: Internal access wait state can be set in CPU rewrite mode. In this time, the following function is
only used.
CPU, ROM, RAM, timer, UART, SI/O2(non-automatic transfer), port
In case of setting internal access wait state, refer to the following explain (software wait).
Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note 2).
A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode
register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus
cycle is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”.
The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit.
Table DA-1 shows the software wait and bus cycles. Figure DA-6 shows example bus timing when
using software waits.
Note 2: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Area
Wait bit
Bus cycle
1
2 BCLK cycles
SFR
Internal
ROM/RAM
0
1 BCLK cycle
Invalid
2 BCLK cycles
Table DA-1. Software waits and bus cycles
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