參數(shù)資料
型號(hào)： M306N0MCT-XXXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 153/158頁
文件大?。?/td> 3298K
代理商： M306N0MCT-XXXXFP
Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
94
Serial I/O
Figure GA-7. Typical transmit/receive timings in clock synchronous serial I/O mode
Example of transmit timing (when internal clock is selected)
Example of receive timing (when external clock is selected)
D0 D1 D2 D3 D4 D5 D6 D7
Tc
TCLK
Stopped pulsing because transfer enable bit = “0”
Data is set in UARTi transmit buffer register
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi's count source (f1, f8, f32)
n: value set to BRGi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
Internal clock is selected.
CTS function is selected.
CLK polarity select bit = “0”.
Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
Cleared to “0” by software, or when an interrupt request is accepted.
Stopped pulsing because CTS = “H”
1 / fEXT
Dummy data is set in UARTi transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
RTSi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UARTi transmit buffer register to UARTi transmit register
Read out from UARTi receive buffer register
Shown in ( ) are bit symbols.
The above timing applies to the following settings.
External clock is selected.
RTS function is selected.
CLK polarity select bit = “0”.
fEXT: frequency of external clock
Transferred from UARTi receive register
to UARTi receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
D0 D1 D2 D3
D4 D5 D6 D7
D0
D1 D2
D3 D4
D5
Transferred from UARTi transmit buffer register to UARTi transmit register
Cleared to “0” by software, or when an interrupt request is accepted.
Meet the following conditions when the CLK input before
data reception = “H”
Transmit enable bit“1”
Receive enable bit“1”
Dummy data write to UARTi transmit buffer register
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