參數(shù)資料
型號： M306N0MCT-XXXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 158/158頁
文件大?。?/td> 3298K
代理商： M306N0MCT-XXXXFP
99
Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Figure GA-12. Typical transmit timings in UART mode
Transmit enablee
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
D0 D1 D2 D3 D4 D5 D6 D7
ST
P
Start
bit
Parity
bit
TxDi
CTSi
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
CTS function is selected.
Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“L”
“H”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi's count source (f1, f8, f32)
fEXT : frequency of BRGi's count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Cleared to “0” by software, or when an interrupt request is accepted.
D0 D1 D2 D3 D4 D5 D6 D7
ST
P
SP
D0 D1
ST
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings :
Parity is disabled.
Two stop bits.
CTS function is disabled.
Transmit interrupt causes select bit = “0”.
Transfer clock
Tc
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi's count source (f1, f8, f32)
fEXT : frequency of BRGi's count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stopped pulsing because transmit enable bit = “0”
Stop
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
D0 D1 D2 D3
D4 D5 D6 D7
STD8
D0 D1 D2 D3 D4 D5 D6 D7
ST
D8
D0 D1
ST
SPSP
Stop
bit
SP
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Data is set in UARTi transmit buffer register
SP
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop
bit
Data is set in UARTi transmit buffer register.
“0”
Cleared to “0” by software, or when an interrupt request is accepted.
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