參數(shù)資料
型號： M306N0MCT-XXXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 114/158頁
文件大?。?/td> 3298K
代理商： M306N0MCT-XXXXFP
59
Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FLD controller
Figure KA-3. Segment/Digit Setting Example
FLD automatic display pins
P0 to P6 are the pins capable of automatic display output for the FLD. The FLD start operating by setting
the automatic display control bit (bit 0 at address 035016) to “1”. There is the FLD output function that
outputs RAM contents from the port every timing or the digit output function that drives the port high with
digit timing. The FLD can be displayed using the FLD output for the segments and the digit or FLD output for
the digits. When using the FLD output for the digits, be sure to write digit display patterns to the RAM in
advance. The remaining segment and digit lines can be used as general-purpose ports. Settings of each
port are shown below.
Table KA-1. Pins in FLD Automatic Display Mode
Port Name Automatic Display Pins
Setting Method
P5, P6
FLD0 to FLD15
P0, P1
FLD16 to FLD31
P2, P3,
FLD32 to FLD51
P44 to P43
P44 to P47
FLD52 to FLD55
The individual bits of the digit output set register (address 035C16,
035D16) can set each pin either FLD port (“0”) or digit port (“1”).
When the pins are set for the digit port, the digit pulse output func-
tion is enabled, so the digit pulses can always be output regardless
the value of FLD automatic display RAM.
FLD exclusive use port (automatic display control bit (bit 0 of ad-
dress 035016)=“1”)
The individual bits of the FLD/port switch register (addresses
035916 to 035B16) can set each pin to either FLD port (“1”) or gen-
eral-purpose port (“0”).
The individual bits of the FLD/port switch register (address 035B16)
can set each pin to either FLD port (“1”) or general-purpose port
(“0”). The digit pulse output function turns to available, and the digit
pulse can output by setting of the FLD output set register (address
035116). The port output format is the CMOS output. When using
the port as a display pin, a driver must be installed externally.
Port P5
Port P0
Number of segments
Number of digits
Port P6
36
16
Port P1
Setting example 1
Shown below is a register setup example where only FLD output is used.
In this case, the digit display output pattern must be set in the FLD automatic
display RAM in advance.
1
FLD32(SEG output)
FLD33(SEG output)
FLD34(SEG output)
FLD35(SEG output)
FLD36(SEG output)
FLD37(SEG output)
FLD38(SEG output)
FLD39(SEG output)
FLD16(SEG output)
FLD17(SEG output)
FLD18(SEG output)
FLD19(SEG output)
FLD20(SEG output)
FLD21(SEG output)
FLD22(SEG output)
FLD23(SEG output)
FLD0(DIG output)
FLD1(DIG output)
FLD2(DIG output)
FLD3(DIG output)
FLD4(DIG output)
FLD5(DIG output)
FLD6(DIG output)
FLD7(DIG output)
0
FLD8(DIG output)
FLD9(DIG output)
FLD10(DIG output)
FLD11(DIG output)
FLD12(DIG output)
FLD13(DIG output)
FLD14(DIG output)
FLD15(DIG output)
0
FLD24(SEG output)
FLD25(SEG output)
FLD26(SEG output)
FLD27(SEG output)
FLD28(SEG output)
FLD29(SEG output)
FLD30(SEG output)
FLD31(SEG output)
Port P2
1
FLD40(SEG output)
FLD41(SEG output)
FLD42(SEG output)
FLD43(SEG output)
FLD44(SEG output)
FLD45(SEG output)
FLD46(SEG output)
FLD47(SEG output)
Port P3
1
0
FLD48(SEG output)
FLD49(SEG output)
FLD50(SEG output)
FLD51(SEG output)
FLD52(port output)
FLD53(port output)
FLD54(port output)
FLD55(port output)
Port P4
Port P5
Port P0
Port P6
28
12
Port P1
Setting example 2
Shown below is a register setup example where both FLD output and digit waveform
output are used. In this case, because the digit display output is automatically
generated, there is no need to set the display pattern in the FLD automatic display RAM.
1
FLD32(SEG output)
FLD33(SEG output)
FLD34(SEG output)
FLD35(SEG output)
FLD36(SEG output)
FLD37(SEG output)
FLD38(SEG output)
FLD39(SEG output)
FLD16(SEG output)
FLD17(SEG output)
FLD18(SEG output)
FLD19(SEG output)
FLD20(SEG output)
FLD21(SEG output)
FLD22(SEG output)
FLD23(SEG output)
FLD0(DIG output)
FLD1(DIG output)
FLD2(DIG output)
FLD3(DIG output)
FLD4(DIG output)
FLD5(DIG output)
FLD6(DIG output)
FLD7(DIG output)
1
FLD8(DIG output)
FLD9(DIG output)
FLD10(DIG output)
FLD11(DIG output)
FLD12(SEG output)
FLD13(SEG output)
FLD14(SEG output)
FLD15(SEG output)
1
0
FLD24(SEG output)
FLD25(SEG output)
FLD26(SEG output)
FLD27(SEG output)
FLD28(SEG output)
FLD29(SEG output)
FLD30(SEG output)
FLD31(SEG output)
Port P2
1
0
FLD40(SEG output)
FLD41(SEG output)
FLD42(SEG output)
FLD43(SEG output)
FLD44(port output)
FLD45(port output)
FLD46(port output)
FLD47(port output)
Port P3
0
FLD48(port output)
FLD49(port output)
FLD50(port output)
FLD51(port output)
FLD52(port output)
FLD53(port output)
FLD54(port output)
FLD55(port output)
Port P4
DIG output
: This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port ( used program).
DIG output
: This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port ( used program).
The contents of digit output set register
(035C16, 035D16)
FLD/port switch register
(035916, 035B16)
Number of segments
Number of digits
The contents of digit output set register
(035C16, 035D16)
FLD/port switch register
(035916, 035B16)
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