參數(shù)資料
型號(hào)： M306N0MCT-XXXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 156/158頁
文件大?。?/td> 3298K
代理商： M306N0MCT-XXXXFP
97
Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART allows transmitting and receiving data after setting the desired transfer rate and transfer data
format. Tables GA-3 lists the specifications of the UART mode. Figure GA-11 shows the UARTi transmit/
receive mode register.
Table GA-3. Specifications of clock synchronous serial I/O mode
Item
Specification
Transfer data format
Character bit (transfer data): 7 bits, 8 bits or 9 bits as selected
Start bit: 1 bit
Parity bit: Odd, even or nothing as selected
Stop bit: 1 bit or 2 bits as selected
Transfer clock
When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :
fi/16(n+1) (Note 1)
fi = f1, f8, f32
When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :
fEXT/16(n+1) (Note 1) (Note 2)
Transmission/reception control
_______
CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition
To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______
- When CTS function is selected, CTS input level = “L”
Reception start condition To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
- Start bit detection
Interrupt request
When transmitting
generation timing
- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register to
UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi receive
buffer register are read out
Framing error
This error occurs when the number of stop bits set is not detected
Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
select function
Sleep mode selection
This mode is used to transfer data to and from one of multiple slave microcomputers
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
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