參數(shù)資料
型號(hào)： M306K9F8LRP
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP144
封裝： 16 X 16 MM, 0.40 MM PITCH, PLASTIC, TQFP-144
文件頁(yè)數(shù)： 65/101頁(yè)
文件大?。?/td> 2590K
代理商： M306K9F8LRP
Interrupt
Rev.1.00
Jun 06, 2003
page 49 of 290
M16C/6K9 Group
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag
to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0”
after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Table.DD-4 Interrupt levels enabled according
to the contents of the IPL
Table.DD-3 Settings of interrupt priority
levels
Interrupt Priority Level Select Bits and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bits in the interrupt control register.
When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is en-
abled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt
priority level to “0” disables the interrupt.
Table.DD-3 shows the settings of interrupt priority levels and Table.DD-4 shows the interrupt levels enabled,
according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
interrupt enable flag (I flag) = 1
interrupt request bit = 1
interrupt priority level > processor interrupt priority level (IPL)
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bits, and the IPL are
independent, and they are not affected each other.
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
0
1
0
1
0
1
0
1
0
1
0
1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
b2 b1 b0
Enabled interrupt priority levels
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL2 IPL1 IPL0
IPL
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