
Reset
Rev.1.00
Jun 06, 2003
page 21 of 290
M16C/6K9 Group
Fig.VB-5 Device's internal status after a reset is cleared (3)
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
(Note1) This register exists only in the flash memory version.
(037D16)
UART2 transmit/receive control register 1
(038016)
Up-down flag
(133)
(038116)
Timer A0 mode register
(134)
(038216)
(135)
(038316)
Timer B0 mode register
Timer B1 mode register
(039916)
Timer B2 mode register
(136)
(038416)
Timer A3 mode register
(137)
(039616)
Timer A4 mode register
(037C16)
UART2 transmit/receive control register 0
0016
0
0016
Timer A1 mode register
(039716)
(131)
0016
(132) Timer A2 mode register
(039816)
0016
0 ?
000 0
00 ?
000 0
00?
0 000
(039A16)
(039B16)
(039C16)
(039D16)
0
00
00 0 0
0
(037816)
UART2 transmit/receive mode register
(129)
(130)
000
1 000
0
000
0 010
0
Trigger select flag
One-shot start flag
Clock prescaler reset flag
Count start flag
0016
(125)
(124)
(126)
(127)
(128)
(123)
UART2 special mode register
(037716)
0016
(121)
(122)
0016
(03E216)
(03E316)
(03E616)
(03E716)
(03EA16)
(03EB16)
(03EE16)
(03EF16)
(03F216)
(03F316)
(03F616)
(03DC16)
(03D616)
(03D716)
(03DE16)
(03D416)
(03FF16)
(03FC16)
(03FD16)
(03FE16)
(150)
(151)
(152)
A-D control register 0
(153)
A-D control register 1
(154) Port P0 direction register
(161)
Port P1 direction register
(162)
Port P2 direction register
(163)
Port P3 direction register
(164)
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Port P8 direction register
Port P9 direction register
Port P10 direction register
D-A control register
(159)
(155)
(156)
(158)
(157)
Comparator control register
(160)
(149) A-D control register 2
(168)
(169)
(170)
(171)
(172)
(173)
(174)
Port control register 0
(175)
Frame base register (FB)
Address registers (A0/A1)
Interrupt table register (INTB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
Data registers (R0/R1/R2/R3)
(176)
(165)
(166)
(167)
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
000
0 ???
0
0016
00
0
00 0
0016
000
0 000
1
0016
000016
0000016
000016
0016
(138)
(139)
(140)
(141)
(03A016)
UART1 transmit/receive control register 0
(146)
(03A416)
UART1 transmit/receive control register 1
(147)
(03A516)
UART transmit/receive control register 2
(148)
(03A816)
DMA0 cause select register
(03AC16)
DMA1 cause select register
0
UART0 transmit/receive mode register
(142)
UART0 transmit/receive control register 0
(143)
UART0 transmit/receive control register 1
(144)
0016
000
1 000
000
0 010
0
UART1 transmit/receive mode register
(145)
0016
000
1 000
000
0 010
0
00 0 0 0
0
0016
(03AD16)
(03B016)
(03B816)
(03BA16)
Flash memory control register (Note1)
00 0 1
(03B716)
Flash memory recognition register (Note1)
1
(03B416)
0
(03A416) 000
1 000
0