參數(shù)資料
型號(hào)： M2V56S30TP-8
廠商： Mitsubishi Electric Corporation
英文描述： 256M Synchronous DRAM
中文描述： 256M同步DRAM
文件頁(yè)數(shù)： 15/49頁(yè)
文件大?。?/td> 244K
代理商： M2V56S30TP-8
Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
15
OPERATIONAL DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-12.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of
open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
READ
A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A0-
9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst
Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ,
WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The
internal precharge starts at the BL after READA. The next ACT command can be issued after (BL +
tRP) from the previous READA. In any case, tRCD+BL
≥
tRASmin must be met.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
READ
ACT
PRE
ACT
Xa
Xb
Yb
Xa
1
Xa
Xb
0
00
01
01
00
Qb0
Qb1
Qb2
Qb3
tRRD
tRCD
tRP
Xa
Precharge All
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