參數(shù)資料
型號(hào)： M2V56S30TP-8
廠商： Mitsubishi Electric Corporation
英文描述： 256M Synchronous DRAM
中文描述： 256M同步DRAM
文件頁(yè)數(shù)： 1/49頁(yè)
文件大?。?/td> 244K
代理商： M2V56S30TP-8
Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
1
M2V56S20TP is a 4-bank x 16777216-word x 4-bit,
M2V56S30TP is a 4-bank x 8388608-word x 8-bit,
M2V56S40TP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz (-7/-8) , 133MHz
(-6), and are suitable for main memory or graphic memory in computer systems.
- Single 3.3v
±
0.3V power supply
- Max. Clock frequency 100MHz(-7/-8), 133MHz (-6)
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
Some of contents are subject to change without notice.
DESCRIPTION
FEATURES
Standard
PC100 (CL3)
PC100 (CL2)
PC133 (CL3)
133MHz
100MHz
77MHz
100MHz
100MHz
100MHz
M2V56S20/30/40TP-8
M2V56S20/30/40TP-7
M2V56S20/30/40TP-6
Max. Frequency
@CL3
Max. Frequency
@CL2
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