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參數(shù)資料
| 型號： | M2V56S30TP-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 256M Synchronous DRAM |
| 中文描述： | 256M同步DRAM |
| 文件頁數(shù)： | 13/49頁 |
| 文件大?。?/td> | 244K |
| 代理商： | M2V56S30TP-8 |
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Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
13
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200
μ
s.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when all banks are
in idle state. After tRSC from a MRS command, the SDRAM is ready
for new command.
/CS
/RAS
/CAS
/WE
BA0,1 A12-A0
CLK
V
R: Reserved for Future Use
BA0 BA1 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
SW
0
0
LTMODE
BT
BL
BURST
LENGTH
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BT=0
1
2
4
8
R
R
R
Full Page
BT=1
1
2
4
8
R
R
R
R
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVED
LATENCY
MODE
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
/CAS LATENCY
R
R
2
3
R
R
R
R
Burst Write
Single Write
SW
0
1
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相關代理商/技術參數(shù) |
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| M2V56S40AKT-5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
| M2V56S40AKT-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Synchronous DRAM |
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