參數(shù)資料
型號: M25P40-VMN6TG/X
廠商: NUMONYX
元件分類: PROM
英文描述: 512K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件頁數(shù): 19/57頁
文件大小: 1160K
代理商: M25P40-VMN6TG/X
Instructions
M25P40
26/57
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 12.
Read Data Bytes (READ) instruction sequence and data-out sequence
1. Address bits A23 to A19 are Don’t Care.
C
D
AI03748D
S
Q
23
2
1
3456789 10
28 29 30 31 32 33 34 35
22 21
3210
36 37 38
76543
1
7
0
High Impedance
Data Out 1
Instruction
24-Bit Address
0
MSB
2
39
Data Out 2
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參數(shù)描述
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