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參數資料
| 型號： | M25P10-AVMB6T/X |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | FLASH 2.7V PROM, DSO8 |
| 封裝： | 2 X 3 MM, ROHS COMPLIANT, UFDFPN-8 |
| 文件頁數： | 51/51頁 |
| 文件大?。?/td> | 1103K |
| 代理商： | M25P10-AVMB6T/X |
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M25P10-A
SPI modes
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Standby mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 3.
Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is selected at a time, so only one device drives the Serial Data output (Q) line at
a time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M25P10-A is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at
the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the tSHCH requirement is met). The
typical value of R is 100 k
Ω, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
AI12836b
SPI bus master
SPI memory
device
SDO
SDI
SCK
CQD
S
SPI memory
device
CQD
S
SPI memory
device
CQD
S
CS3
CS2 CS1
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
RR
R
VCC
VSS
R
相關PDF資料 |
PDF描述 |
|---|---|
| M25P10-AVME3 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P10-AVME3G | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P10-AVME3P | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P10-AVME3T | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P10-AVME3TG | 4 Mbit Uniform Sector, Serial Flash Memory |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M25P10-AVME3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
| M25P10-AVME3G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
| M25P10-AVME3P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
| M25P10-AVME3T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
| M25P10-AVME3TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
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