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參數(shù)資料
| 型號： | M1AGLE3000V2-FGG896I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 70/166頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1KB FLASH 3M 896-FBGA |
| 標準包裝： | 27 |
| 系列： | IGLOOe |
| 邏輯元件/單元數(shù)： | 75264 |
| RAM 位總計： | 516096 |
| 輸入/輸出數(shù)： | 620 |
| 門數(shù)： | 3000000 |
| 電源電壓： | 1.14 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 896-BGA |
| 供應商設備封裝： | 896-FBGA（31x31） |
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IGLOOe Low Power Flash FPGAs
Revision 13
5-5
Revision 6 (Feb 2009)
Product Brief v1.3
The "Pro (Professional) I/O" section was revised to add two bullets regarding
wide range power supply voltage support.
3.0 V was added to the list of supported voltages in the "Pro I/Os with Advanced
Revision 5 (Oct 2008)
Product Brief v1.2
The Quiescent Current values in Table 1 IGLOOe Product Family table were
updated.
Revision 4 (Jul 2008)
Product Brief v1.1
DC
and
Switching
Characteristics
Advance v0.3
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
N/A
Revision 3 (Jun 2008)
DC
and
Switching
Characteristics
Advance v0.2
Tables have been updated to reflect default values in the software. The default
I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V
I/O set.
DDR Tables have two additional data points added to reflect both edges for Input
DDR setup and hold time.
The power data table has been updated to match SmartPower data rather then
simulation values.
N/A
Table 2-144 IGLOOe CCC/PLL Specification was updated to add VMV to the
VCCI parameter row and remove the word "output" from the parameter
description for VCCI. Table note 3 was added.
Table 2-2 Recommended Operating Conditions 1 was updated to include the TJ
parameter. Table note 9 is new.
Temperature1, the maximum operating junction temperature was changed from
110° to 100°.
VMV was removed from Table 2-4 Overshoot and Undershoot Limits 1, 3. The
title of the table was revised to remove "as measured on quiet I/Os." Table note 2
was revised to remove "estimated SSO density over cycles." Table note 3 was
deleted.
The "PLL Behavior at Brownout Condition" section is new.
Levels is new.
EQ 2 was updated. The temperature was changed to 100°C, and therefore the
end result changed.
The table notes for Table 2-9 Quiescent Supply Current (IDD), IGLOOe
Current (IDD) Characteristics, IGLOOe Shutdown Mode* were updated to
remove VMV and include PDC6 and PDC7. VCCI and VJTAG were removed
from the statement about IDD in the table note for Table 2-11 Quiescent Supply
Flash*Freeze Mode1 was updated to include VCCPLL. Note 4 was updated to
include PDC6 and PDC7.
Table note 3 was added to Table 2-13 Summary of I/O Input Buffer Power (per
pin) – Default I/O Software Settings and referenced for 1.2 V LVCMOS.
Revision
Changes
Page
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1AGLE3000V2-FGG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| M1AGLE3000V5-FFG484 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOOE 3M GATES 130NM 1.5V 484FBGA - Trays |
| M1AGLE3000V5-FFG896 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOOE 3M GATES 130NM 1.5V 896FBGA - Trays |
| M1AGLE3000V5-FFG896ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| M1AGLE3000V5-FFG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
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