Revision 13 2-47 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-1" />
參數(shù)資料
型號: M1AGLE3000V2-FGG896I
廠商: Microsemi SoC
文件頁數(shù): 125/166頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 3M 896-FBGA
標(biāo)準(zhǔn)包裝: 27
系列: IGLOOe
邏輯元件/單元數(shù): 75264
RAM 位總計: 516096
輸入/輸出數(shù): 620
門數(shù): 3000000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 896-BGA
供應(yīng)商設(shè)備封裝: 896-FBGA(31x31)
IGLOOe Low Power Flash FPGAs
Revision 13
2-47
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V
applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Table 2-64 Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.2 V
LVCMOS1
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL IIL2 IIH3
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA4
Max.
mA4
A5 A5
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI 2
2
20
26
10 10
Notes:
1. Applicable to V2 devices ONLY.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Figure 2-11 AC Loading
Table 2-65 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
CLOAD (pF)
01.2
0.6
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.
Test Point
Enable Path
Datapath
5 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
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