參數(shù)資料
型號(hào): M13S256328A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 32 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 200萬(wàn)× 32位× 4個(gè)銀行雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù): 31/47頁(yè)
文件大?。?/td> 807K
代理商: M13S256328A
ES MT
M13S256328A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2 31/47
Current State
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Add
Action
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self-Refresh
L
H
L
H
H
H
X
Exit Self-Refresh
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
SELF-REFRESHING*1
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down (Idle after t
PDEX
)
POWER DOWN
L
L
X
X
X
X
X
NOP (Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function True Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Exit Power Down
H
L
L
H
H
H
X
Exit Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
ALL BANKS IDLE*2
L
L
L
X
X
X
X
Refer to Current State = Power Down
H
H
X
X
X
X
X
Refer to Function True Table
ANY STATE other than
listed above
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
Note :
1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must
be satisfied before issuing any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from All Bank Idle state.
相關(guān)PDF資料
PDF描述
M13S32321A 256K x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-6BG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-5BG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-5TG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
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